JPS62152165A - Bipolar transistor manufacturing method - Google Patents

Abstract

PURPOSE:To reduce junction capacitance as the easy takeoff of a base electrode is kept as it is, and to obtain excellent high-frequency characteristics by growing a base layer and an emitter layer in an epitaxial manner onto a partially exposed collector layer in succession again. CONSTITUTION:Collector layers 2, 3, a semi-insulating semiconductor layer 11 and a base layer 4 are formed onto a semi-insulating GaAs substrate 1. An SiO2 film 12 is shaped. One parts of the film 12, the layer 4 and the layer 11 are removed through etching, and one part of the layer 3 is removed. A base layer 5 and emitter layers 6, 7 are grown on the film 12 in an epitaxial manner in succession, and a semi-insulating polycrystalline film is formed to the upper section of the film 11 at that time. One part of the semi-insulating polycrystalline film is etched to expose one parts of the layer 4 and the layer 2. An emitter electrode 10, base electrodes 9 and collector electrodes 9 are each shaped to the layer 7 and the exposed layers 4 and layers 2. According to the method, emitter capacitance is proportional to the junction areas of the layer 6 and the layer 5 in a re-growth section. Consequently, the junction capacitance of the section can be ignored approximately, thus acquiring excellent high-frequency characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 14 is an n-type silicon substrate, 15 is an n + type collector provided thereon by Evita kinial growth, 1G is a p-type base provided by diffusion, 1
7 is an n-type emitter provided by diffusion or alloying;
18 is a collector electrode, 19 is a base electrode, and 2o is an emitter electrode.

Although this is an npn transistor, an np transistor may also be used.

This example uses the same semiconductor material, silicon, to
It forms the emitter, base, and collector.

Incidentally, the operating speed of a transistor, which is related to high frequency characteristics, depends on the transit time of electrons. The base running time is particularly important; the shorter the base length, the faster the operating speed.

Therefore, the shorter the base length, the more desirable it is.
With such a structure, it is actually extremely difficult to reduce the base length to 1000 Å or less while maintaining good ohmic contact in terms of process.

By the way, it is known that when the emitter is formed using a semiconductor having a wider forbidden band energy width than the base (heterojunction bipolar transistor), a very high current gain can be obtained. This is due to the fact that, by choosing materials appropriately, the band structure of the emitter-base junction can be configured so that it does not provide much of a barrier to electrons, but provides a large barrier to holes. A typical example is
It uses AlXGa1□As for the emitter and GaAs for the base and collector.

Furthermore, it is known that such a structure significantly improves high frequency characteristics. The maximum cutoff frequency Fc of a bipolar transistor is determined by Rb: base resistance and CC: collector capacitance. As mentioned above, if the emitter is formed using a semiconductor with higher forbidden band energy than the base,
By choosing materials appropriately, the hand structure of the emitter-base junction can be made to be less of a barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, if the base length is shortened, it is difficult to take out the base electrode, and therefore it is not possible to obtain sufficiently excellent high frequency characteristics.

FIG. 7 shows a conventional example (Japanese Patent Publication No. 55-9830) in which the extraction of the base electrode is improved. In the figure, 21 is an n-type GaAs substrate, 22 is an n-type GaAs substrate forming the collector.
As, 23 is n-type GaAs forming the base, 24 is n-type Δ]xGa, -0ΔS forming the emitter, 25 is p-type Al 1XGa, -XAs for extracting the base electrode.
, 26 is a collector electrode, 27 is a base electrode, and 28 is an emitter electrode.

First, layers 22, 23, and 24 are formed on a GaAs substrate 21 by a liquid phase epitaxial method. Next, a part of the collector layer 22 was exposed by mesa etching, and a p-type AlxGa, -XAs layer for taking out the base electrode 25 was formed on that part again by liquid phase epitaxial method, and electrodes were formed in each. It is.

However, in such a method, traps are likely to be formed between the base layer and the base electrode extraction layer during regrowth. Raising the temperature during regrowth will reduce the number of traps, but interdiffusion of dopants will occur, causing the steepness of the junction to collapse and the characteristics to deteriorate. Therefore, it was not possible to reduce the base resistance so much, and it was practically difficult to obtain a base length of 1000 Å or less.

Furthermore, since the junction area between the p-type base layer and the n-type collector layer is large and the collector capacitance is large, it was not possible to obtain sufficiently excellent high frequency characteristics (as seen from equation 11).

Further, in this conventional example, the area of the emitter portion is larger than the area of the emitter electrode due to mask alignment.

In other words, the junction area between the p-type base layer and the n-type emitter is larger than the emitter electrode area, so the bending of the electrode has an emitter base junction capacitance, that is, the emitter capacitance lce.
was big.

By the way, the maximum frequency Ft at which the 1i current amplification factor of the transistor is 1 is Ft= (1/2ff) ・ (A-Ce+B)-'
......(2) Given by A, B, constants. (S, M, Sze; Physicsor
Sem1conductor Devices,
John Wiley & 5ons.

I n c, , pp, 283. 1969)
Therefore, if the emitter capacitance Ce is large, high frequency characteristics are poor.

In this conventional method, if the emitter is formed on the substrate side and the collector is formed on the upper side, the collector capacitance becomes large in proportion to the area of the electrode, which is also unfavorable for high frequency characteristics as seen from equation (1).

Further, in the case of the structure of this conventional example, the area of the emitter electrode is smaller than the area of the emitter and groove due to mask alignment as described above. The area of the emitter electrode should be as large as possible. This is because the contact resistance of the electrode is proportional to its area, and the contact resistance slows down the charging time for the transistor capacity, which also reduces the high frequency characteristics.

Problems to be Solved by the Invention With such a conventional configuration, it is difficult to obtain an element with a short base length, low resistance, small collector capacitance and emitter capacitance, and low electrode contact resistance, and the high frequency characteristics I don't get what I paid for.

The present invention is advantageous in these respects, and has an extremely short and low base length while maintaining the ease of removing the hemi-sumi scraper, furthermore has small collector capacitance and emitter capacitance, and is also related to high frequency characteristics. The purpose is to provide a structure with low electrode contact resistance, which becomes series resistance.

Means for Solving the Problems In order to solve the above problems, the present invention provides a thick base electrode extraction layer which is separated from the collector (or emitter) by a semi-insulating semiconductor layer and has an insulating film thereon. By forming and etching an anti-adhesive film,
After removing a portion of the nuclear base electrode extraction layer and the antimicrobial insulating semiconductor layer, an extremely thin base layer and an emitter (or By growing a semi-insulating polycrystalline film on the top of the anti-adhesive film, the booth length can be extremely short and low while maintaining the ease of taking out the base electrode, and the collector capacitance can be reduced. and small emitter capacitance,
Furthermore, it provides a structure with low electrode contact resistance.

Operation The present invention has an extremely short and low base length, and also has a small collector capacitance and emitter capacitance due to the above-described structure.
Furthermore, since the electrode contact resistance is low, high frequency characteristics are improved.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In FIG. 1, 1 is a semi-insulating Ga, As substrate,
2 is an n-type GaAs collector with one layer (T; scraped layer), 3 is an n-type GaAs collector with two layers, and 4 is a p-type G5As
Heath 1 layer (electrode extraction layer), 5 is p-type (:, aAs base 2 layers, 6 is n-type Alx Ga 1-x As
(X=O-3) Emitter 1 layer, 7 is n+ type GaA
S emitter, 2 layers (electrode extraction layer), 8 is collector electrode,
9 is a base electrode, 10 is an emitter layer, 11 is GaAs
It is a semi-insulating semiconductor layer. 12 is a SiO2 insulating film;
5.6.7 The shaded area at the top of 12 is half because it was formed on S i O21i! ! It is a polycrystalline 11 that has been converted to Xi.

The thickness of each layer is 400 μm for l semi-insulating GaAS substrate.
, 2 n-type GaAs collector 1 layer has 4000 people, 3 n-type GaAs collector 2 layer has 2000 people, 4 p-type Ga
As Heath 1 layer 5000 people, 5 p-type GaAs base 2
400 layers, 500 layers per layer of 6 n-type AlXGa1-xAsAs emitters, 7 n+ type Gafi for electricity extraction,
The number is 1,500 for the second S emitter layer, and 2,000 for the 11 GaAs semi-insulating semiconductor layers.

Each layer of 2 to 7.11 is formed using molecular beam epitaxy (MBE).
formed by. 12 S+02 films are 1000
It is human and was formed by chemical vapor deposition.

Next, a method for manufacturing the device of this example will be described.

As shown in FIG. 2, first, layers of 2.3.degree. and 11.4 degrees were formed to a predetermined thickness on a semi-insulating GaAs substrate 1 by molecular beam epitaxy. Next, by chemical vapor deposition, 1
A SiO2 film of 2 was formed to a thickness of 2,000 people.

Next, a resist mask is formed by a conventional photolithography method, and as shown in FIG. A part of the collector 2 layer of No. 3 was exposed by etching. In this case, the etching may proceed to the inside of the collector layer, as shown by the dotted line in FIG. Etching of SiO□IIQ is done with hydrofluoric acid, etching of Qa and As is done with H2'
The experiment was carried out using a mixed solution of So, -H20□-H20. G
By using (OO1) as an aAs substrate, (
The etched portion could be formed in the shape of an inverted trapezoid as shown in FIG. 3 when viewed from the 110) direction.

Next, the resist was removed with acetone, and SiO was removed with hydrochloric acid.
After removing 1,000 layers of layer 2, a part of the P-type base electrode extraction layer of layer 4 was located as shown in FIG.

Next, by molecular beam epitaxy, 400 layers of p-type GaAS base and 1500 layers of n-type Al were formed on top of the whole.
One layer of xGa, -xAs emitters and two layers of 1500 n+ type GaAs emitters were regrown as shown in FIG.

Next, by photolithography, a part of the anti-adhesive membrane was removed with 11□So, -H20□H20? Notching was performed using a mixture of n and hydrochloric acid to expose a portion of the base 1 layer and the collector 1 layer.

Next, the resist portion was removed using 77 tons, and by ordinary photolithography, vacuum evaporation, and heat treatment techniques, an emitter electrode of lO was formed on the emitter 2 grown on the exposed base and collector layer. A base fipi and a collector electrode of 9.8 in diameter were formed respectively.

The emitter capacity of the structure of this embodiment is proportional to the junction area between the emitter and the base of the regrowth portion. In the case of this embodiment, the area is the sum of the area of the junction epitaxially grown on the exposed collector layer and the area of the polycrystalline film junction grown on the insulation +19. In this example, 13e is used to form the p-type base of No. 5 and doped with 1.10θ/cod, and Si is used to form the emitter layer of No. '-ping was carried out. However, the obtained polycrystalline one showed a high I resistance of 106 ohms and was semi-insulating. Therefore, the junction capacitance in this part can be almost ignored. The area of the emitter base junction is almost the same as the area of the exposed collector and can be minimized.Also, even if the emitter electrode is made larger than the area of the emitter epitaxial growth area, short circuits and parasitic capacitance may occur due to the semi-insulating nature of the polycrystalline film. Such problems do not occur.

In other words, it has a self-line structure including a collector, an emitter, and an emitter/vine electrode. Therefore, the emitter electrode can be formed over the entire emitter region. Since the contact resistance is proportional to the area of the junction with the electrode, this allows the emitter contact resistance to be minimized.

Reducing the series resistance speeds up the charging time for the capacitance, which greatly contributes to improving the cylinder circumference and characteristics.

The collector capacitance of the structure of this example and CC are Pn of 5 and 3.
This is the sum of the junction capacitance of the junction and the junction capacitance of the junctions 11 and 3.

In general, the capacitance Cpn of a p-n junction is... (3) a; junction area q; charge NAI; acceptor concentration ND2 of the I) type semiconductor; donor concentration εl of the n-type semiconductor; dielectric constant ε2 of the p-type semiconductor ; Dielectric constant of n-type semiconductor ■b; Given by bias voltage.

From this, it can be seen that when the difference between the acceptor concentration and the donor concentration is large, it is determined approximately by the smaller one.The acceptor concentration of the p-type GaAs base layer in this example is 1.10''/cd. , the donor concentration of the n-type GaAs collector layer is 5.10''/Cta. Therefore, the collector capacitance is approximately.

On the other hand, the junction capacitance between the n-type GaAs layer and the semi-insulating GaAs layer is 1.101 when the semi-insulating layer has 7 cubic meters/storey.
5/c++I or less, the junction capacitance is proportional to the square root of this acceptor concentration, and its value is much smaller than the value of equation (4). If there is no semi-insulating layer, the junction capacitance between 11 and 3 will be as large as 1.101 I/d, so the collector capacitance of this portion will be large. P-type GaAs
Even if p-type AIX Ga1-X As is used instead, the junction capacitance remains almost unchanged. For the above reasons, as in this embodiment, by forming a semi-insulating layer between the GaAs layer for protruding the p-type base electrode and the n-type GaAs collector layer, if the structure has the same size, Collector capacity can be much smaller.

Furthermore, the base length of the structure of this example is extremely short, 400 people. Transit time ts of electrons in bipolar transistor
is known to be approximately expressed as follows. (W, P.

Dumke et al:5-olid 5tat
eElectron,, vol, 15. no
. 12゜pp, 1339. Dec, 1972
)ts= (5/2)Rh−Cc+ (Rb/RL
)・ cb+ (3Cc+CL) RL・・・・
・(5) RL; Load resistance tb: Base running time CC; Load capacity On the other hand, the base running time is t b = L b / Ve −
f61Lb; Base length ■e; Given by the speed of electrons in Hebe.

In this example, by taking advantage of the characteristics of a heterojunction bipolar transistor, the carrier concentration in the base region is made extremely high (a carrier concentration of 1.10"/Cta is used in the example). Since the thickness of the parts other than the base is 5,000 mm thick, the permeability resistance associated with drawing out the base can be extremely low.Furthermore, if the manufacturing method of this embodiment is used, it is extremely easy to draw out even an extremely thin base. .

As described above, according to the method of this embodiment, emitter capacitance Fi (Ce, collector capacitance Cc, base resistance Rh,
Since the base length Lb and the series contact resistance can all be reduced at the same time, it is possible to obtain a transistor with excellent high frequency characteristics and an extremely high maximum cutoff frequency.

The heterojunction transistor obtained in this example exhibited the following characteristics as expected. First, we were able to form good ohmic electrodes on a very thin base made of 400 people. As a result, the travel time to the destination was shortened. Furthermore, the collector capacitance and emitter capacitance have also become smaller. Furthermore, the base resistance and electrode contact resistance have also been reduced. From the above, when the emitter area is made the same size, the high frequency characteristics are greatly improved compared to the conventional one.

In this example, an example of 400 base lengths is shown, but it is possible to make the base length even thinner by using molecular beam epitaxy technology. A similar thin base can also be created using the CVD method.

In this example, SiO2 was used as the insulating film, but S
Similar results have been obtained with iN, and any insulating film on which a semiconductor is not epitaxially grown may be used.

Further, in this example, GaAs-AlXGa is used as the semiconductor.
, -XAs, but other semiconductor materials such as InP
It can also be created using -1nGaAsP or the like.

Also, x = 0.3 was used as the AI concentration, which is O
It can be arbitrarily selected within the range of -1.

In this example, GaAs was used as the semi-insulating layer, but
It is clear that even if A is larger than that of GaAs, so leakage current can be reduced. Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

In this embodiment, the emitter and collector are of n-type and the base is of p-type, but the emitter and collector may be of p-type and the base of n-type.

In this embodiment, the collector is formed on the substrate side and the emitter is formed on the upper part, but it is also possible to form the emitter on the substrate side and the collector on the upper part by a similar manufacturing method. In this case, the above discussion can be considered by replacing Ce and Cc, and it is clear that both Ce and Cc can be made smaller in this case as well.

In this case, the contact resistance of the collector electrode is reduced instead of that of the emitter electrode, which is also effective in accelerating charging of the capacitance and has a similar effect in improving high frequency characteristics.

Effects of the Invention As described above, the present invention significantly shortens the base length and lowers the resistance while maintaining the ease of taking out the base electrode, further reduces the collector capacitance and emitter capacitance, and further reduces the contact resistance. By doing so, a bipolar transistor with excellent high frequency characteristics is provided.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a transistor using a method for manufacturing a bipolar transistor according to an embodiment of the present invention, and FIG.
FIG. 5 is a cross-sectional view of the manufacturing process, FIG. 6 is a cross-sectional view of a conventional bipolar transistor, and FIG. 7 is a cross-sectional view of a conventional heterojunction transistor. l...5 semi-insulating GaAs plates, 2...
n+GaAs collector (or emitter) 1 layer ('electrode extraction layer), 3... n-type GaAs collector (
or emitter) 2 layers, 4. old... p-type Ga to S base 1 layer (TL electrode extraction layer), 5... p-type GaA
s-base 2 layers, 6...n-type GaAs emitter (
or collector) lI'3.7...n 10G
a A s Emitter (or collector) 21ffl (electrode extraction layer), 8... Collector (or emitter) electrode, 9... Base electrode, 10...
・Emitter (or collector) electrode, 11...
-GaAs semi-insulating semiconductor layer, 12...insulating film, 13...resist. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 □ = 1 21', 15 1/4''?3

Claims (4)

[Claims] (1) After forming a collector (or emitter) layer on a semiconductor substrate, a semi-insulating semiconductor layer and a base electrode extraction layer are sequentially epitaxially grown on it, and an insulating film is further formed on it, and then the insulating layer is formed on the semiconductor substrate. After removing a part of the film, the base electrode extraction layer, and the semi-insulating semiconductor layer by etching to expose a part of the collector (or emitter) layer, a base layer, an emitter (or collector) layer are formed thereon, and a part of the collector (or emitter) layer is exposed. ) layers are sequentially grown epitaxially, and at that time, a semi-insulating polycrystalline film is grown on top of the insulating film to reduce the emitter (or collector)-base junction capacitance and to separate the epitaxially grown emitter (or collector) from other parts. An emitter (or collector) electrode is formed on the entire upper surface of the emitter (or collector) part, and a part of the semi-insulating polycrystalline film is etched to form an emitter (or collector) electrode on the entire upper surface of the base layer and the collector. A method for manufacturing a bipolar transistor, characterized in that a part of a (or emitter) layer is exposed, and a base electrode and a collector (or emitter) electrode are formed on each layer. (2) The method for manufacturing a bipolar transistor according to claim (1), wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. (3) A method for manufacturing a bipolar transistor according to claim (1), characterized in that a III-V compound semiconductor is used. (4) The method for manufacturing a bipolar transistor according to claim (1), characterized in that silicon oxide or silicon nitride is used as the insulating film.