JP2580281B2 - Bipolar transistor element - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a homojunction bipolar transistor using GaAs, which has a horizontal structure suitable for planarization and a current amplification factor of It concerns a large element.

(Prior art)

Bipolar transistors have higher current driving capability than field-effect transistors (FETs), and thus have attracted attention as circuit elements for operating circuits with large loads at high speed. In particular, a compound semiconductor such as GaAs has an electron mobility higher than that of silicon, and is therefore advantageous in utilizing the high speed of a bipolar transistor.

Conventionally, the mainstream of the development of bipolar transistors using GaAs as the main material is a transistor that uses a material with a wide band gap consisting of three elements of aluminum, gallium, and arsenic and has a heterojunction between the emitter and base. However, such a heterojunction bipolar transistor is about to be put into practical use. The reason why the heterojunction bipolar transistor has been developed is that this structure enables a high concentration of base impurities without lowering the Emit injection efficiency, so that the base resistance is reduced and a high-speed device can be realized.

On the other hand, a homojunction bipolar transistor in which the emitter is composed of the same GaAs as the base and collector has not received much attention in the past, but has the following advantages as compared with the heterojunction bipolar transistor.

(1) Since an n-type layer and a p-type layer can be formed by diffusing or ion-implanting impurities into a commercially available GaAs substrate, it is relatively simple without using a complicated epitaxial growth apparatus such as a heterojunction bipolar transistor. Can be manufactured.

(2) Conventional silicon bipolar transistor technology or MESFET technology without using a heterojunction can be easily diverted, and is suitable for large-scale circuit production and mass production.

(3) Since there is no recombination current in the depletion layer due to the trap level in the aluminum / gallium / arsenic compound semiconductor, the device characteristics are excellent in stability and reproducibility.

Despite these features, homojunction bipolar transistors made of GaAs were not widely used because the emitter injection efficiency decreased as the base impurity concentration was increased to improve the characteristics, and sufficient current gain was obtained. This is because it cannot be obtained.

One of the drawbacks of the heterojunction transistor is that it is not suitable for manufacturing a lateral transistor. Lateral transistors, that is, devices in which the emitter-base junction and base-collector junction are formed perpendicular to the substrate surface, are easier to manufacture than vertical transistors because the emitter, base, and collector electrodes can be removed from the surface. Suitable for large-scale integration.

[Problems to be solved by the invention]

However, it is difficult to realize a lateral transistor by a molecular beam epitaxy method or a metal organic chemical vapor deposition method, which is a crystal growth technique for fabricating the above-mentioned heterostructure, because the heterostructure is formed in a direction perpendicular to the substrate. It is.

Therefore, a homojunction bipolar transistor is required for manufacturing a lateral transistor, and an increase in the current amplification factor of this element is an important issue.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a lateral homojunction bipolar transistor having a lateral structure suitable for integration, and capable of improving a decrease in emitter injection efficiency and sufficiently increasing a current amplification factor even if a base resistance is reduced. is there.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a bipolar transistor element comprising a GaAs single crystal substrate having semi-insulating or n-type (p-type) conductivity, wherein the orientation of the surface of the GaAs single crystal substrate is ( 111) The planes perpendicular to the plane, ie (1, −1,0), (1,0, −1), (−1,1,0), (−1,1,0)
Within the crystal of the (0,1), (0,1, -1), and (0, -1,1) planes, an n-type GaAs conductive layer, a p-type GaAs conductive layer, Is set so that an n-type GaAs layer is provided adjacent to this order, the emitter-base junction surface is parallel to the (111) plane, and electrons and holes mainly flow in the [111] direction. Is the most important feature.

[Action]

According to the above-described means, the current amplification factor can be made larger than that of the conventional homojunction bipolar transistor, so that the base layer can be made thinner and more concentrated, and the high-frequency characteristics of the transistor can be improved. Further, since the transistor is a horizontal transistor, it is suitable for planarization, and a large-scale integrated circuit can be manufactured.

[Principle of the invention]

Hereinafter, the principle of the bipolar transistor element formed of a GaAs single crystal substrate having semi-insulating or n-type (p-type) conductivity according to the present invention will be described.

Cutoff frequency, a performance index of bipolar transistors
ft and the maximum oscillation frequency fmax are respectively expressed as follows.

Here, τ _{E in} equation (1) is the emitter charging time, τ _B is the base traveling time, τ _C is the collector traveling time, and τ ' _C is the collector charging time. Further, r _b is the base resistance, C _C is the collector capacitance.

τ _B represents the time for carriers to diffuse in the base region, and is a major factor that determines the value of ft. This τ _B
Is, if the base width is W and the diffusion constant of the carrier is D,
In the case of a uniform impurity base, it is given by τ _B = W ² / 2D. Therefore, in order to increase ft, it is necessary to make the base thinner and shorten the carrier traveling time. On the other hand, when thinning the base width base resistance r _b is increased, it can be seen that the reduction in the maximum oscillation frequency fmax from equation (2).

From the above, in order to improve the high frequency characteristics,
It is necessary to reduce the base resistance value by reducing the thickness of the base layer and increasing the impurity concentration of the base layer.

In the bipolar transistor, the performance indicators Another important is the current amplification factor h _FE, the current amplification factor h _FE of the emitter grounding circuit in the DC _{operation, h FE = γα T M /} (1-γα T M) … (3) Here, γ: emitter injection efficiency α _T : base transport efficiency M: collector doubling coefficient. Normally, the base transport efficiency and the collector doubling coefficient are close to “1”, so that the current amplification factor can be approximated to γ / (1−γ). Therefore, for an npn transistor, _Therefore , the current amplification factor h _FE is n _B: the minority carriers (electrons) concentration p _E in the base: the minority carriers (holes) concentration D _B in the emitter: minority carriers (holes) diffusion constant D _E in the base: the minority carriers (holes in the emitter ) Diffusion constant L _B : Diffusion length of minority carriers (electrons) in base L _E : Diffusion length of minority carriers (holes) in emitter.

By the way, there is a relationship of D = kTμ / q (k: Boltzmann constant, T: absolute temperature, q: charge of the carrier) between the diffusion constant D and the mobility μ of the carrier. Then Holds, the current amplification factor h _FE is Becomes Here, μ _nB : mobility of electrons in base μ _pB : mobility of holes in emitter τ _nB : lifetime of electrons in base τ _pE : lifetime of electrons in emitter.

As is apparent from equation (5), the current amplification factor h _FE is inversely proportional to the square root of the mobility of holes in the emitter, and this mobility is 3/2 power of the effective mass m * of holes. Is inversely proportional to It can be seen that the current amplification factor increases in proportion to the 3/4 power of the effective mass of holes. That is, in order to increase the current amplification factor h _FE can by increasing the effective mass of a hole.

Since the effective mass is related to the second derivative of the energy band in k-space, the same material may have different values depending on the crystal orientation. In GaAs, Hayakawa et al. Reported that the effective mass of heavy holes differs between the [111] and [100] orientations, and m _hh * [111] = 0.9m ₀ , m _hh * [100]. = 0.34m ₀ , is reported. Where m ₀ is the mass of the electron in free space (Trothy Hayakawa et al., Physical
Review Letters, Vol. 60, No. 4, pp. 349-352).

Therefore, the heavy hole to exercise the [111] orientation reduced mobility, the result (6) As can be seen from the equation, the current amplification factor h _FE of the homojunction bipolar transistor increases. According to Hayakawa et al., The effective mass of a light hole does not change, and is m _lh * [111] = m _lh * [100] = 0.117 m ₀ .

Effective mass m * considering both heavy and light holes
Is given by m * = (m _hh * ^3/2 + _mlh * ^3/2 ) ^2/3 . From this equation, the effective mass in the [111] and [100] directions is m * [111] = 0.93. _{m 0 m * [100] =} 0.38m 0 next, m * [111] is about 2.5 times the m * [100].
Therefore, the current amplification factor _hFE increases by a factor of 2 according to the equation (6).

FIG. 5 compares the current amplification factor of a homojunction bipolar transistor fabricated on a (100) plane GaAs and a homojunction bipolar transistor fabricated on a (111) plane as a function of the base impurity concentration. Here, the calculation is performed in consideration of the band gap reduction due to the high concentration doping.

As is clear from FIG. 5, the base concentration at which the same current amplification factor is obtained is about twice as large in the (111) plane.
It can be seen that this orientation is advantageous for increasing the base concentration.

FIG. 6 shows that the impurity concentration of the emitter and the base is 1 × 10 ¹⁸
9 shows the relationship between the current amplification factor h _FE and the base width when cm ^-3 is set. As shown in FIG. 6, in the transistor manufactured on the (111) plane, the current amplification factor h _FE is as large as 300 even at the base width of 500 °, and the _hFE decreases due to the surface recombination. In this case, it is considered that practically sufficient current amplification is possible.

As described above, in GaAs, the current amplification factor of a bipolar transistor set to allow carriers to flow in the [111] direction can be increased.

In a GaAs single crystal, a homojunction bipolar transistor in which the emitter-base junction is arranged parallel to the (111) plane has a large current amplification factor. Suitable for miniaturization,
High-speed transistors can be obtained.

(Example of the invention)

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

[Example I]

FIG. 1 is a sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example I of the present invention.

As shown in FIG. 1, the lateral homojunction bipolar transistor according to the first embodiment has a surface perpendicular to the (111) plane, that is, (1, −1,0), (1,0, −1), (−). 1,1,0), (−
N-type Ga having (0,1, -1), (0,1, -1) and (0, -1,1) planes
On an As substrate 107, an n-type emitter layer 105, a p-type base layer 106, and an n ⁺ -type collector contact layer 104 are formed, and electrode layers 101, 102, and 103 are formed thereon, and a collector electrode C, an emitter electrode E, This is a lateral homojunction bipolar transistor having a base electrode B.

1A, 1B, 1C, and 1D are cross-sectional views showing a schematic configuration in each manufacturing process of the lateral homojunction bipolar transistor shown in FIG.

First, as shown in FIG. 1A, the lateral homojunction bipolar transistor of Example I is formed by ion implantation using an SiO ₂ film 111 as a mask on an n-type GaAs substrate 107 having a surface perpendicular to the (111) plane. P-type layer 11 by a thermal or thermal diffusion method
Form 2. Next, as shown in FIG. 1B, a part of the SiO ₂ film 111 is removed, and a new SiO ₂ film 113 is formed. next,
As shown in FIG. 1C, an Si ₃ N ₄ film 114 is formed thereon, and an n-type emitter layer 105 is formed therethrough by ion implantation. At this time, the n ⁺ -type collector contact layer 104 is also formed at the same time.

By using the side wall of the Si ₃ N ₄ film 114, the thickness of the base layer is reduced. Finally, the ion implantation layer is activated, and further, as shown in FIG. 1D, the electrode layers 101, 102, 103
To form

A similar transistor can be manufactured by epitaxially growing an n-type layer on a semi-insulating GaAs substrate instead of the n-type substrate and using this layer.

(Example II)

FIG. 2 is a sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example II of the present invention.

As shown in FIG. 2, the lateral homojunction bipolar transistor of Example II uses a p-type substrate 206 as a base layer and forms an n-type emitter layer 204 and a collector layer 205 by ion implantation or thermal diffusion. Then, an emitter electrode 201 and a collector electrode 203 are formed on them, and Si ₃ N ₄
FIG. 2 is a cross-sectional view of a lateral homojunction bipolar transistor having a base electrode 202 formed on a film (not shown).
FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, and FIG. 2E are cross-sectional views showing a schematic configuration in each manufacturing process of the lateral homojunction bipolar transistor shown in FIG.

In the lateral homojunction bipolar transistor of Example II, as shown in FIG. 2A, a Si ₃ N ₄ film 211 is formed on a p-type GaAs substrate 206 having a surface perpendicular to the (111) plane. Then, an FPM resist layer 212, an SiO ₂ film 213, and an AZ resist layer 214 are formed. Next, as shown in FIG. 2B, the uppermost AZ resist layer 214 is patterned, and the SiO ₂ film 213 and the FPM resist layer 212 are removed by a reactive ion etching method. Next, ion implantation is performed through the Si ₃ N ₄ film 211 to form n-type layers 204 and 205. Next, as shown in 2C Figure, SiO ₂ film 2
Form 15. Next, as shown in 2D view, SiO ₂ film 213
After removing the side wall layer with buffer hydrofluoric acid, the FPM resist layer 2
12 is lifted off with an organic solvent, and SiO _{4 is formed into the} shape shown in FIG. 2D.
A film 215 is formed. Next, after activating the ion implantation layer, the SiO ₂ film 215 and the Si ₃ N ₄ film 211 are removed by etching to form the emitter electrode 201 and the collector electrode 203. Finally, the Si ₃ N ₄ film 211 is removed by plasma etching to form the base electrode 202.

It should be noted that, instead of the p-type substrate 206, a P-type layer is epitaxially grown on a semi-insulating GaAs substrate, and a transistor can be manufactured in the same process using this layer.

(Example III)

FIG. 3 is a sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example III of the present invention.

As shown in FIG. 3, the lateral homojunction bipolar transistor of Example III has a p-type GaAs layer 308 having a surface perpendicular to the (111) plane and a p-type AlGaAs layer 307 and a high-resistance Al layer.
It has a structure sandwiched between GaAs layers 309 to reduce carrier recombination on the surface and leakage current to the semi-insulating GaAs substrate 306. In FIG. 3, reference numeral 301 denotes an emitter electrode, 302 denotes a base electrode, 303 denotes a collector electrode, and 304 and 305 denote n-type layers (collector layer and emitter layer).

(Example IV)

FIG. 4 is a sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example IV of the present invention.

The lateral homojunction bipolar transistor of Example IV has a p-type layer formed on a multilayer epitaxial layer by an ion implantation method or a thermal diffusion method.

That is, as shown in FIG. 4, a semi-insulating GaAs substrate 410 having a surface perpendicular to the (111) plane is provided with a high-resistance AlGaA
s layer 409, n-type GaAs layer 408, n-type AlGaAs layer 407, p-type AlGaAs
The layer 405 and the p-type GaAs layer 404 are epitaxially grown.

FIGS. 4A, 4B, 4C, 4D and 4E show FIG.
It is sectional drawing which shows schematic structure in each manufacturing process of the horizontal homojunction bipolar transistor shown in a figure.

As a manufacturing process of the lateral homojunction bipolar transistor of Example IV, first, as shown in FIG. 4A, an n-type GaAs layer 408 is epitaxially grown on a semi-insulating GaAs substrate 410, and Then, after forming a SiO ₂ film 411 and patterning with a resist layer 412, as shown in FIG.
The SiO ₂ film 411 is removed by reactive ion etching. Next, as shown in FIG. 4C, a Si ₂ N ₄ film 413 is formed, and as shown in FIG. 4D, a p-type base layer 414 is formed by ion implantation through the Si ₃ N ₄ film 413. By passing the Si ₃ N ₄ film 413, the base layer thickness is reduced. In this step, a p-layer can be formed by a thermal diffusion method without using the Si ₃ N ₄ film 413.

Next, the ion implantation layer is activated. Finally, as shown in FIG. 4E, an n-layer is exposed by mesa etching to form an emitter electrode 401 and a collector electrode 403, and a base electrode
402 is formed on the p-type GaAs layer 414. However, Fig. 4A,
4B, 4C, 4D, and 4E, the mesa etching shape, the high-resistance AlGaAs layer 409, the n-type AlGaAs layer 407, and the p-type
The AlGaAs layer 405 and the p-type GaAs layer 404 are not shown.

As mentioned above, although the present invention was explained concretely based on an example, the present invention is not limited to the above-mentioned example.
It goes without saying that various changes can be made without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, the current amplification factor can be made larger than that of the conventional homojunction bipolar transistor, so that the base layer can be thinned and the concentration can be increased, and the high-frequency characteristics of the transistor can be improved. be able to.

Further, since the transistor is a horizontal transistor, it is suitable for planarization, and a large-scale integrated circuit can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example I of the present invention. FIGS. 1A, 1B, 1C and 1D are lateral homojunction bipolar transistors shown in FIG. FIG. 2 is a cross-sectional view showing a schematic configuration in each manufacturing process of the bipolar transistor; FIG. 2 is a cross-sectional view showing a schematic configuration of a lateral homojunction bipolar transistor according to Example II of the present invention; FIG. 2A, FIG. 2B, and FIG. 2D and 2E are cross-sectional views showing a schematic configuration in each manufacturing process of the lateral homojunction bipolar transistor shown in FIG. 2. FIG. 3 is a sectional view of the lateral homojunction bipolar transistor according to Embodiment III of the present invention. FIG. 4 is a cross-sectional view showing a schematic configuration of the lateral homojunction bipolar transistor according to Example IV of the present invention; FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, and FIG. The figure shows the horizontal homozygous Sectional view showing a schematic configuration of each manufacturing process of the over La transistor, Fig. 5, the conventional (100) homojunction bipolar transistor and the emitter-base junction fabricated in GaAs substrate (11
1) A diagram showing the relationship between the current amplification factor and the base impurity concentration for a homojunction bipolar transistor as a surface. FIG. 6 shows a conventional homojunction bipolar transistor fabricated on a (100) GaAs substrate and an emitter-base junction. Is (11
1) A diagram showing a relationship between a current amplification factor and a base width for a homojunction bipolar transistor serving as a surface. In the figure, 101, 201, 301, 401 ... emitter electrode, 102, 202, 30
2,402 base electrode, 103, 203, 303, 403 collector electrode, 104 collector contact layer, 204, 304 contact layer, 105, 205, 305 emitter layer, 106 base layer, 107 n-type GaAs substrate, 111, 113, 213, 215, 411…
SiO ₂ film, 112 p-type layer, 206 p-type GaAs substrate, 114, 21
1,413: Si ₃ N ₄ film, 212: FPM resist layer, 214: AZ
Resist layer, 306, 410 ... Semi-insulating GaAs substrate, 308,404,4
11 p-type GaAs layer, 307, 405 p-type AlGaAs layer, 407
n-type AlGaAs layer, 408: n-type GaAs layer, 309, 409: high resistance
AlGaAs layer, 412: resist layer.

Claims (1)

(57) [Claims] (1) having semi-insulating or n-type (p-type) conductivity;
A bipolar transistor element comprising a GaAs single crystal substrate, wherein the surface orientation of the GaAs single crystal substrate is perpendicular to the (111) plane, that is, (1, −1,0), (1,0, −).
1), (-1,1,0), (-1,0,1), (0,1, -1), (0,
A GaAs layer having n-type conductivity, a GaAs layer having p-type conductivity, and a GaAs layer having n-type conductivity are provided adjacent to each other in this order within the crystal of the (−1,1) plane, and A bipolar transistor element, wherein an emitter-base junction surface is parallel to a (111) plane and electrons and holes are set to flow mainly in a [111] direction.