JP2001257364A - Diode, diode array, and manufacturing method of the diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a diode having proper element-characteristics and a proper high-frequency characteristic, and which can be produced easily at a low price using a simple process. SOLUTION: On flat portions 1a, 1c and an inclined portion 1b of a GaAs substrate 1, which comprise respectively (311) A planes and a (100) A plane, GaAs layers, doped with Si of an amphoteric impurity, are formed respectively by epitaxial growths. Thereby, p-type layers 2a, made of p-type GaAs formed on the flat portions 1a, 1c existing on the GaAs substrate 1, and an n-type layer 2b made of n-type GaAs is formed on the inclined portion 1b existing on the GaAs substrate 1. By having n-type carriers included in the n-type layer 2b diffuse into the p-type layer 2a, a compensation region 2c is formed in the portion of the p-type layer 2a, which is present in the vicinity of the interface between the p-type layer 2a and the n-type layer 2b. Furthermore, a p-electrode 3 is formed on the p-type layer 2a, and an n-electrode 4 is formed on the n-type layer 2b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diode usable in a microwave band or a millimeter wave band in a very high frequency range, a diode array using the diode, and a method of manufacturing the diode.

[0002]

2. Description of the Related Art A mixer diode having a cutoff frequency (cut-off frequency) of 100 GHz to 1 THz is manufactured by a point contact diode or a planar Schottky diode on an n-type GaAs substrate.

A point contact diode has a high series resistance, a large leakage current, and a gentle reverse voltage breakdown (soft), but has the advantage of having a high cutoff frequency due to a small junction capacitance. However, it is difficult to produce a uniform diode array consisting of a plurality of point contact diodes.

On the other hand, a planar Schottky diode is
Although the series resistance is lower than that of the point contact diode, it is difficult to obtain a sufficiently small junction according to the conventional photolithography, so that it is difficult to obtain high-frequency performance equivalent to that of the point contact diode.

[0005] IEEE TRANSACTIONS ON MICROWAVE T
HEORY AND TECHNIQUES, VOL. 46, NO.11, NOVEMBER 199
8, pp. 1976-1981, proposes a method for fabricating a diode array composed of planar Schottky diodes by a process including electron beam lithography and formation of a metal air bridge.

[0006]

As described above, the conventional point contact diode has good high frequency performance, but has a high series resistance, a large leakage current, and it is difficult to produce a uniform diode array. is there.

On the other hand, the conventional planar Schottky diode is superior in element performance such as series resistance and leakage current as compared with the point contact diode, but is inferior in high frequency characteristics as compared with the point contact diode. In addition, complicated and expensive processes such as electron beam lithography and formation of a metal air bridge are required to produce a diode array.

It is an object of the present invention to provide a diode having good device performance and high-frequency characteristics, which can be easily and inexpensively manufactured, and a method of manufacturing the same.

Another object of the present invention is to provide a uniform diode array which has good element performance and high-frequency characteristics and can be easily and inexpensively manufactured.

[0010]

Means for Solving the Problems and Effects of the Invention A diode according to a first aspect of the present invention provides an insulated compound semiconductor substrate having a main surface having a first plane orientation, which is tilted with respect to the first plane orientation. An inclined surface having a second plane orientation is formed, and an epitaxial growth layer made of a compound semiconductor doped with an amphoteric impurity is formed in a region extending from the principal surface to the inclined surface, whereby the first surface is formed on the principal surface. A first compound semiconductor of a conductivity type is formed, a second compound semiconductor layer of a second conductivity type is formed on the inclined surface, and a first electrode electrically contacting the first compound semiconductor layer; Second electrodes are formed so as to be in electrical contact with the second compound semiconductor layer.

In a diode according to the present invention, a compound semiconductor in which an amphoteric impurity is doped in a region extending from a main surface having a first plane orientation to an inclined surface having a second plane orientation of an insulating compound semiconductor substrate. Is formed. The amphoteric impurity becomes the first conductivity type impurity on the main surface having the first plane orientation, and becomes the second conductivity type impurity on the inclined surface having the second plane orientation. Thereby, the first compound semiconductor layer of the first conductivity type is formed on the main surface, and the second compound semiconductor layer of the second conductivity type is formed on the inclined surface. The first and second first and second compound semiconductor layers are in electrical contact with each other.
And a second electrode. In this way,
A lateral (lateral) pn junction is formed in the epitaxial growth layer on the insulating compound semiconductor substrate.

The area of the junction region is given by the thickness of the first and second compound semiconductor layers and the width of the first and second compound semiconductor layers. By reducing the thickness of the first and second compound semiconductor layers, the junction capacitance can be reduced. Further, by adjusting the concentration of the amphoteric impurity doped into the first and second compound semiconductor layers, the value of the series resistance can be adjusted. Thereby, the series resistance can be reduced and the high frequency characteristics can be improved. Further, the leakage current can be reduced by adjusting the width of the first and second compound semiconductor layers. Further, since the ratio between the width and the thickness of the bonding region is large, the heat radiation characteristics are improved. Thereby, it is possible to process a large amount of power.

Further, since the diode according to the present invention can be formed on an insulating compound semiconductor substrate by a planar technique, a uniform diode array composed of a plurality of diodes can be easily and inexpensively manufactured by a simple process. It becomes possible.

The insulating compound semiconductor substrate is a III-V group compound semiconductor substrate, and the amphoteric impurity is made of a group IV element.
The epitaxial growth layer may be made of a III-V compound semiconductor.

In this case, the amphoteric impurity comprising a group IV element doped into the epitaxial growth layer may be a first conductivity type impurity or a second conductivity type impurity depending on the first and second plane orientations of the III-V compound semiconductor substrate. Works as an impurity.

The III-V compound semiconductor substrate may be a gallium arsenide substrate. Further, the group IV element may be silicon or germanium.

[0017] A compensation region may be formed near the interface between the first compound semiconductor layer and the second compound semiconductor layer by diffusion of the first conductivity type impurity or the second conductivity type impurity. Thereby, the junction capacitance is further reduced.

The combination of the first plane orientation and the second plane orientation is (311) A plane, (100) A plane, and (111) A plane.
Plane and (311) A plane, (211) A plane and (100) A
Plane, or (100) A plane and (311) A plane.

When the first plane orientation and the second plane orientation have any combination of these, the amphoteric impurity functions as the first conductivity type impurity on the main surface having the first plane orientation, and Amphoteric impurities on the inclined surface having
It acts as a conductive impurity.

The diode array according to the second invention has a plurality of diodes according to the first invention formed on an insulating compound semiconductor substrate.

Since the diode according to the first aspect of the present invention can be formed by a planar technique, a uniform diode array composed of a plurality of diodes on an insulating compound semiconductor substrate can be easily realized at low cost.

According to a third aspect of the present invention, there is provided a diode manufacturing method, wherein an insulating compound semiconductor substrate having a main surface having a first plane orientation is provided with a second plane orientation inclined with respect to the first plane orientation. Forming an inclined surface having a first conductivity type on the main surface by epitaxially growing a compound semiconductor layer doped with amphoteric impurities in a region extending from the main surface to the inclined surface of the insulating compound semiconductor substrate. Forming a second compound semiconductor layer of the second conductivity type on the inclined surface while forming the first compound semiconductor layer; and forming the first electrode and the second electrode in electrical contact with the first compound semiconductor layer. Forming a second electrode that is in electrical contact with the compound semiconductor layer.

In the method of manufacturing a diode according to the present invention, a region extending from the main surface having the first plane orientation to the inclined surface having the second plane orientation of the insulating compound semiconductor substrate is doped with the amphoteric impurity. The formed compound semiconductor layer is formed by epitaxial growth. The amphoteric impurity becomes the first conductivity type impurity on the main surface having the first plane orientation, and becomes the second conductivity type impurity on the inclined surface having the second plane orientation. Thereby, the first compound semiconductor layer of the first conductivity type is formed on the main surface, and the second compound semiconductor layer of the second conductivity type is formed on the inclined surface. Then, first and second electrodes that are in electrical contact with the first and second compound semiconductor layers, respectively, are formed. In this manner, the compound semiconductor layer on the insulating compound semiconductor substrate has
A -n junction is formed.

In the diode manufactured by this manufacturing method, the area of the junction region is given by the thickness of the first and second compound semiconductor layers and the width of the first and second compound semiconductor layers. By reducing the thickness of the first and second compound semiconductor layers, the junction capacitance can be reduced. Further, by adjusting the concentration of the amphoteric impurity doped into the first and second compound semiconductor layers, the value of the series resistance can be adjusted. Thereby, the series resistance can be reduced and the high frequency characteristics can be improved. Further, the leakage current can be reduced by adjusting the width of the first and second compound semiconductor layers. Further, since the ratio between the width and the thickness of the bonding region is large, the heat radiation characteristics are improved. Thereby,
Large power can be processed.

Further, according to the diode manufacturing method of the present invention, since a plurality of diodes can be formed on the insulating compound semiconductor substrate by the planar technique, a uniform diode array including the plurality of diodes can be easily formed. It can be manufactured easily and inexpensively in the process.

[0026]

FIG. 1 is a schematic sectional view of a diode according to an embodiment of the present invention, and FIG. 2 is a schematic plan view of the diode of FIG. This diode is used, for example, as a mixer diode for mixing a plurality of frequencies.

The diode 100 shown in FIG. 1 is formed on a semi-insulating GaAs substrate 1. The GaAs substrate 1
It has a step composed of flat portions 1a and 1c having a plane orientation (311) A plane and an inclined portion 1b having a plane orientation (100) A plane.

A p-type layer 2a of p-type GaAs is formed on the flat portions 1a and 1c of the GaAs substrate 1 by epitaxial growth, and an n-type layer 2b of n-type GaAs is formed on the inclined portion 1b by epitaxial growth. ing. In the present embodiment, thickness t of p-type layer 2a and n-type layer 2b is 100 nm. Also, as shown in FIG.
The width W of the p-type layer 2a and the n-type layer 2b is 200 μm.

The p-type layer 2a and the n-type layer 2b are doped with amphoteric impurity Si (silicon) as a dopant. The carrier concentration of p-type layer 2a and n-type layer 2b is 5 × 10 ¹⁸ cm ⁻³ . (31) of the GaAs substrate 1
1) At the time of epitaxial growth of a GaAs layer on the A-plane, Si becomes a p-type impurity, and (100) of the GaAs substrate 1
When epitaxially growing a GaAs layer on the A-plane, S
i becomes an n-type impurity.

Thus, the flat portion 1 on the GaAs substrate 1
A p-type layer 2a made of p-type GaAs is formed on a and 1c, and an n-type layer 2b made of n-type GaAs is formed on the inclined portion 1b. Thus, a lateral pn junction (lateral pn junction) is formed.

The p near the interface between the p-type layer 2a and the n-type layer 2b
A compensation region 2c is formed in the mold layer 2a. The compensation region 2c is formed by diffusing n-type carriers (electrons) in the n-type layer 2b having higher mobility than p-type carriers (holes) into the p-type layer 2a. In the compensation area 2c,
The carrier concentration changes slowly. In the present embodiment, the thickness L of the compensation region 2c is 0.5 μm.

On the upper p-type layer 2a, a p-electrode 3 made of ZnAu is formed. An n-electrode 4 made of AuGe / Ni / Au is formed from a region on the n-type layer 2b to a region on the lower p-type layer 2a. p electrode 3 and n electrode 4
Is preferably equal to the thickness L of the compensation region 2c. However, since it is difficult to perform alignment so that the n-electrode 4 does not cover the pn junction, in practice, the p-electrode 3 The gap g between the gate electrode and the n-electrode 4 is larger than the thickness L of the compensation region 2c as shown in the figure. In the present embodiment, the gap g is ideally 0.5 μm.

In the diode 100 shown in FIG. 1, the cross section of the compensation region 2c between the p-type layer 2a and the n-type layer 2b is a junction region. The area of the junction region is the thickness t of the compensation region 2c.
And the width W of the compensation region 2c, which is 100 nm × 200 μm in the present embodiment.

In the diode 100 of FIG. 1, the p-type layer 2a
Since the thickness t of the n-type layer 2b can be reduced to about several tens of nm, the junction capacitance can be made equal to or smaller than the point contact diode. Further, the presence of the compensation region 2c further reduces the junction capacitance.

By adjusting the dopant concentration (carrier concentration) of the p-type layer 2a and the n-type layer 2b,
The value of the series resistance can be adjusted. Thereby, the series resistance can be reduced. Also, by adjusting the value of the series resistance so that the RC time constant is minimized,
High frequency performance can be improved. For example, it is possible to improve the cutoff frequency to about 10 THz.

Further, the leakage current can be reduced by adjusting the width W of the junction region. Further, since the aspect ratio between the width W and the thickness t of the bonding region is large, the heat radiation characteristics are improved. Thereby, it is possible to process larger power.

Next, a method of manufacturing the diode 100 shown in FIG. 1 will be described. 3 and 4 illustrate the diode 100 of FIG.
It is a schematic process sectional drawing which shows the manufacturing method of this.

First, as shown in FIG. 3, a part of the GaAs substrate 1 having the (311) A plane is etched by wet etching to thereby form the inclined portion 1b of the (100) A plane and the (311) A plane. A step composed of the flat portions 1a and 1c is formed.

Next, as shown in FIG.
A GaAs layer is grown on the flat portions 1a and 1c and the inclined portion 1b by MBE (molecular beam epitaxy). At this time, the GaAs layer is doped with Si, which is an amphoteric impurity. The conductivity type of the GaAs layer doped with Si depends on the plane orientation, and becomes p-type on the (311) A plane and n-type on the (100) A plane.

Thus, the p-type layer 2a made of p-type GaAs is formed on the flat portions 1a and 1c of the GaAs substrate 1, and the n-type layer 2b made of n-type GaAs is formed on the inclined portion 1b.
Is formed. Further, the compensation region 2c is formed in the p-type layer 2a near the interface between the p-type layer 2a and the n-type layer 2b due to the diffusion of the n-type carriers. After that, element isolation is performed by photolithography and wet etching.

Finally, as shown in FIG. 1, a p-electrode 3 made of AuGe is formed on the upper p-type layer 2a by a lift-off method.
Is formed, and an n-electrode 4 made of AuGe / Ni / Au is formed on the n-type layer 2b and the lower p-type layer 2a by a lift-off method.

As described above, the diode 1 of the present embodiment
00 can be easily and inexpensively manufactured by a planar technique such as ordinary photolithography, etching and epitaxial growth.

When the characteristics of the diode 100 of this embodiment were calculated, the junction capacitance was 1.2 fF and the series resistance was 25 Ω. The cutoff frequency is 5.5
THz, which was higher than that of the point contact diode.

FIGS. 5, 6, 7 and 8 show the relationship between the conductivity type and the plane orientation of the Si-doped GaAs layer formed on the GaAs substrate.

In the example of FIG. 5, (311) G having the A plane
An inclined portion composed of a (100) A plane is formed on the aAs substrate 11 by etching. In this case, Si epitaxially grown on the (311) A surface of the GaAs substrate 11
The doped GaAs layer 21 becomes p-type, and the GaAs substrate 11
The Si-doped GaAs layer 22 epitaxially grown on the (100) A plane becomes n-type.

In the example of FIG. 6, G having a (111) A plane
An inclined portion composed of the (311) A plane is formed on the aAs substrate 12 by etching. In this case, Si grown epitaxially on the (111) A plane of the GaAs substrate 12
The doped GaAs layer 23 becomes p-type and the GaAs substrate 12
The (311) Si-doped GaAs layer 24 epitaxially grown on the A-plane becomes n-type.

In the example of FIG. 7, the G having the (211) A plane
An inclined portion composed of a (100) A plane is formed on the aAs substrate 13 by etching. In this case, Si epitaxially grown on the (211) A surface of the GaAs substrate 13
The doped GaAs layer 25 becomes p-type and the GaAs substrate 13
The Si-doped GaAs layer 26 epitaxially grown on the (100) A plane becomes n-type.

In the example of FIG. 8, G having a (100) A plane
An inclined portion composed of the (311) A plane is formed on the aAs substrate 14 by etching. In this case, Si that is epitaxially grown on the (100) A plane of the GaAs substrate 14
The doped GaAs layer 27 becomes n-type and the GaAs substrate 14
The (311) Si-doped GaAs layer 28 epitaxially grown on the A-plane becomes p-type.

The diode 100 shown in FIG. 1 and FIG.
However, the example of FIG. 6, FIG. 7, or FIG. 8 may be applied to the diode of the present invention.

FIG. 9 shows the diode 100 of FIGS.
FIG. 2 is a schematic plan view showing an example of a diode array using the device. This diode array can be used as a detector (antenna) for detecting an electric field.

As shown in FIG. 9, on a GaAs substrate 1,
A plurality of diodes 100 are arranged in a matrix in the direction of arrow X (hereinafter, referred to as X direction) and in the direction of arrow Y (hereinafter, referred to as Y direction).

The n of the plurality of diodes 100 arranged in the X direction
The electrodes 4 and the p-electrodes 3 are connected by a wiring layer 200. Of the two diodes 100 adjacent in the Y direction, the n-electrode 4 of one diode 100 and the p-electrode 3 of the other diode 100
00 is connected.

At one end of the GaAs substrate 1 in the Y direction, the p-electrodes 3 of the plurality of diodes 100 arranged in the X direction are connected by a wiring layer 201. GaA
At the other end in the Y direction on the s-substrate 1, the n-electrodes 4 of the plurality of diodes 100 arranged in the X direction are connected by a wiring layer 202.

In manufacturing the diode array of FIG. 9,
(311) The inclined portion 1b composed of the (100) A plane shown in FIG. 1 is formed on the GaAs substrate 1 having the A plane by etching, and a Si-doped GaAs layer is epitaxially grown on the GaAs substrate 1 to obtain the structure shown in FIG. P-type layer 2a and n-type layer 2b can be formed simultaneously.

As described above, a uniform diode array can be easily and inexpensively manufactured by simple steps of photolithography, etching and epitaxial growth.

Although Si is used as the amphoteric impurity in the above embodiment, Ge (germanium) may be used instead of Si.

In the above embodiment, GaAs is used as the material of the p-type layer 2a and the n-type layer 2b.
AlGaAs as a material for the p-type layer 2a and the n-type layer 2b
Various III-V compound semiconductors such as s and InP can be used.

Further, in the above embodiment, the p-type layer 2a
And the n-type layer 2b is formed by the MBE method.
Another epitaxial growth method such as an OCVD method (metal organic chemical vapor deposition) may be used.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a diode according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of the diode of FIG.

FIG. 3 is a schematic cross-sectional view showing a step of the method for manufacturing the diode in FIG.

FIG. 4 is a schematic process sectional view illustrating the method of manufacturing the diode in FIG. 1;

FIG. 5 shows a Si-doped GaAs formed on a GaAs substrate.
FIG. 4 is a diagram illustrating an example of a relationship between a conductivity type of an s layer and a plane orientation.

FIG. 6 shows a Si-doped GaAs formed on a GaAs substrate.
FIG. 4 is a diagram illustrating an example of a relationship between a conductivity type of an s layer and a plane orientation.

FIG. 7: Si-doped GaAs formed on a GaAs substrate
FIG. 4 is a diagram illustrating an example of a relationship between a conductivity type of an s layer and a plane orientation.

FIG. 8 shows a Si-doped GaAs formed on a GaAs substrate.
FIG. 4 is a diagram illustrating an example of a relationship between a conductivity type of an s layer and a plane orientation.

FIG. 9 is a schematic plan view of a diode array using the diodes of FIGS. 1 and 2;

[Explanation of symbols]

 1,11,12,13,14 GaAs substrate 1a, 1c Flat portion 1b Inclined portion 2a, 21,23,25,28 p-type layer 2b, 22,24,26,27 n-type layer 2c compensation region 3p electrode 4 N electrode 100 Diode 200, 201, 202 Wiring layer

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[Procedure amendment]

[Submission Date] January 12, 2001 (2001.1.1)
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction contents]

Although Si is used as the amphoteric impurity in the above embodiment, a group IV element is used instead of Si.
Ge the (germanium) may be used that.

Claims (8)

[Claims] An insulating compound semiconductor substrate having a main surface having a first plane orientation, wherein an inclined surface having a second plane orientation inclined with respect to the first plane orientation is formed on the insulating compound semiconductor substrate; An epitaxial growth layer made of a compound semiconductor doped with an amphoteric impurity is formed in a region extending from the surface to the inclined surface, so that a first conductivity type first semiconductor layer is formed on the main surface.
And a second compound semiconductor layer of a second conductivity type is formed on the inclined surface, and the first electrode and the second electrode which are in electrical contact with the first compound semiconductor layer are formed. A second electrode electrically connected to the compound semiconductor layer. 2. The method according to claim 1, wherein the insulating compound semiconductor substrate is III-V.
2. The diode according to claim 1, wherein said diode is a group III compound semiconductor substrate, wherein said amphoteric impurity comprises a group IV element, and said epitaxial growth layer comprises a group III-V compound semiconductor. 3. The diode according to claim 2, wherein said III-V compound semiconductor substrate is a gallium arsenide substrate. 4. The diode according to claim 2, wherein said group IV element is silicon or germanium. 5. A compensation region is formed near an interface between the first compound semiconductor layer and the second compound semiconductor layer by diffusion of a first conductivity type impurity or a second conductivity type impurity. The diode according to claim 1. 6. A combination of the first plane orientation and the second plane orientation includes a (311) A plane and a (100) A plane,
(111) A plane and (311) A plane, (211) A plane and (100) A plane, or (100) A plane and (311) A plane
The diode according to claim 2, wherein the diode is a surface. 7. An insulating compound semiconductor substrate according to claim 1, wherein
7. A diode array, wherein the plurality of diodes according to any one of 6 are formed. 8. A step of forming an inclined surface having a second plane orientation inclined with respect to the first plane orientation on an insulating compound semiconductor substrate having a main surface having a first plane orientation; A first compound semiconductor of a first conductivity type is formed on the main surface by epitaxially growing a compound semiconductor layer doped with an amphoteric impurity in a region extending from the main surface to the inclined surface of the insulating compound semiconductor substrate. Forming a layer and forming a second compound semiconductor layer of a second conductivity type on the inclined surface; a first electrode electrically contacting the first compound semiconductor layer and the second compound Forming a second electrode which is in electrical contact with the semiconductor layer.