JPS61294862A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a structure, in which a collector capacity is small, by forming a semi-insulating semiconductor layer, removing a part of the semi- insulating semiconductor layer by etching, and regrowing a base layer and an emitter layer thereon. CONSTITUTION:On a semi-insulating GaAs substrate 1, layers 2-4 are formed to specified thicknesses. A part of the AlGaAs semi-insulating semiconductor layer 4 is etched, and a part of the collector 2 layer 3 is exposed. Resist is removed with acetone. The P-type GaAs base layer, the N-type AlGaAs emitter 1 layer and the N<+> type GaAs emitter 2 layer are grown again. Then, a part of a certain part of the semi-insulating semiconductor layer is etched. A part of the base layer and a part of the collector layer are exposed. The resist part is removed with acetone. An emitter electrode 10 is formed at a part, where the semi-insulating semiconductor layer is not present. A base electrode 9 and a collector electrode 8 are formed on the exposed base and collector layers. Thus, the collector capacity can be made very small, and excellent high frequency characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor with excellent high frequency characteristics.

Prior Art A typical structure of a conventional bipolar transistor is shown in FIG. In the figure, 12 is an n-type silicon substrate, 13 is an n+ type collector provided thereon by epitaxial growth, 14 is a p-type base provided by diffusion, 1
6 is an n-type emitter provided by diffusion or alloying;
16 is a collector electrode, 17 is a base electrode, and 18 is an emitter electrode.

Although this is an npn transistor, a pnp transistor may also be used.

This example uses the same semiconductor material, silicon, to
It forms the emitter, base, and collector.

By the way, it is known that when the emitter is formed using a semiconductor having a wider forbidden band energy width than the base (heterojunction bipolar transistor), a very high current gain can be obtained. This is because, by selecting materials appropriately, the band structure of the emitter-base junction can be configured so that it does not provide a weak barrier to electrons but provides a large barrier to holes. A typical example is
The emitter is made of 1xCtIL1-xAS, and the base and collector are made of GaAs.

Furthermore, it is known that such a structure can significantly improve high frequency characteristics. The maximum cutoff frequency Fc of a bipolar transistor is Fc = * / (2iRb(jc ding (1)
Rb i Base resistance CC: Arrayed by collector capacitance. If the emitter is formed using a semiconductor with a large forbidden band energy as well as the base, as mentioned above,
By appropriately selecting the material, the band structure of the emitter-base junction can be modified so that it does not become a barrier to electrons.
It can be configured to provide a large barrier to holes. Therefore, the carrier concentration (hole concentration) of the base can be made very high. Therefore, the base resistance can be made extremely small, and as a result, a very large maximum cutoff frequency Fc can be obtained. However, the junction area between the p-type base layer and the n-type collector layer is large, and the collector capacitance is large. Because of the large value, it was not possible to obtain sufficiently excellent high frequency characteristics as shown in equation (1).

Problems to be Solved by the Invention With such a conventional configuration, it is difficult to obtain an element with a small collector capacitance, and it is not possible to obtain an element with sufficiently excellent high frequency characteristics.

The present invention was made in view of this point, and an object of the present invention is to provide a structure with a small collector capacitance.

Means for Solving the Problems In order to solve the above problems, the present invention forms a semi-insulating semiconductor layer in advance, removes a part of the semi-insulating semiconductor layer by etching, and forms a base layer on top of the semi-insulating semiconductor layer. A structure with a small collector capacitance is provided by regrowing the emitter layer using an epitaxial growth technique such as molecular beam epitaxy.

Effects The present invention improves high frequency characteristics because the collector capacitance is small due to the above-described structure.

Example FIG. 1 shows an embodiment of the structure of the present invention.

In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is an n+
1 layer of type GaAS collector (electrode extraction layer), 3 is n-type GaAs=r collector 2 layers, 4 is mullyG & 1ym5
(y=o, 3) semi-insulating semiconductor layer, 6 is p-type GaAs base layer, 6 is n-type multilayer lx Ga 1 + xA s (
o, a) One emitter layer, 7 an n-type GaAs x emitter two layers (electrode extraction layer), 8 a collector electrode, 9 a base electrode, and 10 an emitter electrode.

The thickness of each layer is 400 pm for 1 semi-insulating GaAs substrate.
, 2's n-type GaAs collector layer is 400OA.

3. The n-type GaAg collector 2 layer is 20oOm, 4.mu.J.
yG&1-amS semi-insulating semiconductor layer at 200oX.

6 p type G&S base layer is 1000 people, 6 n type M'
! "1-X Bx emitter 1 layer has a thickness of 1600 µm, and the n-type Ga 2-type S emitter 2 layer for electrode extraction at 7 has a thickness of 16 QoX. Each layer from 2 to 7 is formed using molecular beam epitaxy (MBIE).
formed by.

Next, a method for manufacturing the device of this example will be described.

As shown in FIG. 2, layers 2 to 4 were first formed to a predetermined thickness on a semi-insulating GaAs substrate 1 by molecular beam epitaxy. Next, a resist mask is formed by a conventional photolithography method, and a part of the 4% Ga1-As semi-insulating semiconductor layer is etched using this resist mask, as shown in FIG. , collector 2 of 3
Part of the layer was exposed. In this case, the etching may proceed to the inside of the collector layer, as shown by the dotted line in FIG. MuJyGa4. For etching As, H2SO
, -H2O2-H20 mixture was used. GaA
By using (001) as the g substrate, [11
0] It was possible to form an etched portion in the shape of an inverted trapezoid as shown in FIG. 3 when viewed from the direction.

Next, the resist was removed with acetone, and by molecular beam epitaxy, a p-type GILA8 base layer of 1oooX and a
tsooX n-type muno, a1, ABx mitter 1 layer,
Two 1500 µm n-type GaAs x-mitter layers were regrown as shown in FIG.

Next, by photolithography, a certain portion of the semi-insulating semiconductor layer is etched using a H2SO4-H2O2-H20 mixed solution, and the base layer and the collector 1 are etched.
Part of the layer was exposed.

Next, the resist part was removed with acetone, and an emitter electrode of 1° was formed on the part without the semi-insulating semiconductor layer using ordinary photolithography, vacuum evaporation and heat treatment techniques.
A 9.8 base electrode and a collector electrode were formed on the exposed base and collector layers, respectively.

The collector capacitance Cc of the structure of this embodiment is the sum of the junction capacitance of the pn junctions 6 and 3 and the junction capacitance of the junctions 4 and 3.

Generally, the capacitance Cpn of a pn junction is a; Joint area q; electric charge Nmu1; acceptor concentration of p-type semiconductor Donor concentration of HD2Hn type semiconductor Dielectric constant of ε1ip type semiconductor Dielectric constant of ε2in type semiconductor Vbi bias voltage is given by

This is the difference between acceptor concentration and donor concentration.

It can be seen that when the magnitude is larger, it is determined approximately by the smaller of the magnitudes. In this example, the acceptor concentration of the p-type GaM S base layer is 1-10'nd, and the donor concentration of the n-type GaM S collector layer is 5.1 o17/d! It is.

Therefore, the collector capacity is approximately ap・-Ji7 (3).

On the other hand, the junction capacitance between the n-type GaAs layer and the Munoa Ga1-AmS semi-insulating semiconductor layer is determined by the square root of this acceptor concentration, since the acceptor concentration of the semi-insulating semiconductor layer is 1·1017 ci or less. is proportional to, and its value is
It is much smaller than the value of equation (3). If there is no semi-insulating semiconductor layer, the junction capacitance between 4 and 3 is
The carrier concentration of the n-type GaAs layer is 1·1018/aA
Since this is large, the collector capacity of this part becomes large. p-type aluminum alloy Ga1-xAs instead of p-type GaAg
Even if , the junction capacitance remains almost the same. For the above reasons, as in this embodiment, the p-type base layer and the n-type gap
By forming a semi-insulating semiconductor layer between the s-collector layer and the s-collector layer, the collector capacitance can be made much smaller if the structure has the same area. If the collector capacity becomes smaller, (
According to equation 1), it is clear that the high frequency characteristics are improved.

In this example, the carrier concentration in the base region can be extremely high by taking advantage of the characteristics of a heterojunction bipolar transistor (a carrier concentration of 1.1 o19/d is used in the example), so the base resistance Rh is extremely small. So,
Therefore, a transistor with extremely high maximum cutoff frequency and high frequency characteristics can be obtained.

As expected, the collector capacitance of the heterojunction transistor obtained in this example was significantly reduced;
When the dimensions are the same, the high frequency characteristics are greatly improved compared to the conventional one.

Although the molecular beam epitaxy technique was used in this embodiment, it can be similarly formed by using, for example, a metal organic chemical vapor deposition (MO-CVN) method.

In addition, in this example, the semiconductor is a GaAs-based 1xGaAs semiconductor.
1-. Although As was used, other semiconductor materials, such as InP
- It can also be created using InGaAsP or the like.

Further, as the mulch concentration, X=0.3.7=0.3 was used, but this can be arbitrarily selected within the range of 0 to 1.

In this example, λayGa1-amS is used as the semi-insulating layer.
It is clear that using (0,3) or using y=o, that is, GaAs, has the same effect in terms of reducing the collector capacitance.

In this example, 7=0.3 was used, but Mu! A GIL1
-AmS has a larger forbidden band energy than GlLAs, so that the leakage current between the GaAs layer for counting the p-type base electrode and the n-type collector layer can be further reduced. Since leakage current reduces the current amplification factor of the transistor, the current amplification factor can be improved by reducing the leakage current.

In this example, a [-V compound semiconductor was used, but a bipolar transistor with an extremely small collector capacitance could be obtained using silicon (Si) using a similar process using molecular beam epitaxy. The obtained S1 bipolar transistor also showed excellent high frequency characteristics.

In this embodiment, the emitter and collector are n'lJl and the base is p type, but the emitter and collector can be p type and the base can be n type.

Effects of the Invention As described above, the present invention provides a bipolar transistor with excellent high frequency characteristics by significantly reducing the collector capacitance.

[Brief explanation of drawings]

Figure 1 is a diagram showing an embodiment of the present invention, Figures 2 to 4 are diagrams showing a structure in the process of being manufactured to realize the structure of the present invention, and Figure 6 is a diagram showing the structure of a conventional bipolar transistor. FIG. 1...-semi-insulating GILAS substrate, 2...
・n + GaAs collector 1 layer (electrode extraction layer),
3...N-type G & Mu S collector 2 layers, 4...
...Muly@tt1. As semi-insulating semiconductor layer, 6...
...p-type Gamus base layer, 6...n Saint'
! "1-X S emitter 1 layer, 7...n+Ga
As emitter 2 layers (electrode number υ layer), 8...
Collector electrode, 9...Base electrode, 10...
...Emitter electrode, 11...Resist. Name of agent: Patent attorney Toshio Nakao and one other person C-
-Eng. 5ff ff Figure 2

Claims (4)

[Claims] (1) After forming a collector layer on a semiconductor substrate and forming a semi-insulating semiconductor layer thereon, a part of the semi-insulating semiconductor layer is removed to expose a part of the collector layer. , a base layer and an emitter layer are sequentially grown epitaxially thereon, and then an emitter electrode is formed on the emitter layer formed in the part where the semi-insulating semiconductor layer is not, and a part where the semi-insulating semiconductor layer is. 1. A method of manufacturing a bipolar transistor, comprising: removing a portion of the base layer and exposing a portion of the collector layer, and forming a base electrode and a collector electrode thereon. (2) The method for manufacturing a bipolar transistor according to claim 1, wherein at least the forbidden band energy width of the emitter is larger than the forbidden band energy width of the base. (3) The method for manufacturing a bipolar transistor according to claim 1, wherein the forbidden band energy width of the semi-insulating semiconductor layer is larger than that of the base. (4) A method for manufacturing a bipolar transistor according to claim 1, characterized in that a III-V compound semiconductor is used.