JP2854634B2 - Light receiving device - Google Patents

Light receiving device

Info

Publication number
JP2854634B2
JP2854634B2 JP1307724A JP30772489A JP2854634B2 JP 2854634 B2 JP2854634 B2 JP 2854634B2 JP 1307724 A JP1307724 A JP 1307724A JP 30772489 A JP30772489 A JP 30772489A JP 2854634 B2 JP2854634 B2 JP 2854634B2
Authority
JP
Japan
Prior art keywords
compound semiconductor
type
junction
semiconductor substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1307724A
Other languages
Japanese (ja)
Other versions
JPH03169084A (en
Inventor
均 中村
昌一 花谷
千秋 野津
創 大歳
宏司 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Japan Display Inc
Original Assignee
Hitachi Device Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Device Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Device Engineering Co Ltd
Priority to JP1307724A priority Critical patent/JP2854634B2/en
Publication of JPH03169084A publication Critical patent/JPH03169084A/en
Application granted granted Critical
Publication of JP2854634B2 publication Critical patent/JP2854634B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光通信システム等に用いるアンバランシエフ
オトダイオード(APD)の構造,製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a structure and a manufacturing method of an avalanche photodiode (APD) used for an optical communication system or the like.

〔従来の技術〕[Conventional technology]

現在、光通信に用いられるAPDの基本構造はノイズ,
暗電流を低減させるため第2図に示したような光吸収層
と増倍層を空間的に分離した構造が主流である。その
際、素子の高速化,ノイズ低減の点から重要な事は、増
倍層に注入されるキヤリアの種類である。すなわち、電
子に対するイオン化率αとホールに対するイオン化率β
の比であるイオン化率比k(=α/β)が、1より大き
い場合には電子注入が、また1より小の場合にはホール
注入が望ましい。
At present, the basic structure of APD used for optical communication is noise,
In order to reduce dark current, a structure in which a light absorption layer and a multiplication layer are spatially separated as shown in FIG. 2 is mainly used. At that time, what is important in terms of increasing the speed of the element and reducing noise is the type of carrier injected into the multiplication layer. That is, the ionization rate α for electrons and the ionization rate β for holes
When the ionization rate ratio k (= α / β), which is the ratio, is larger than 1, electron injection is desirable, and when it is smaller than 1, hole injection is desirable.

第2図(a)はホール注入型素子の、また同図(c)
は電子注入型素子の従来構造の模式図である。(a),
(b)の具体例としては、それぞれInP/InGaAs系APD,Ga
As/GaAlAs超格子APD〔セミコングクターズ アンド セ
ミメタルズ(Semicorductors and Semimetals)Vol.22
p117(1985)アカデミツク プレス インコーポレーテ
ツド(Academic Press Inc.)〕等がある。同図におい
て黒丸印(●)及び白丸印(○)は波線で示した光によ
り光吸収層内に生じた電子、およびホールを示し、矢印
は、APD動作時のそれぞれのキアリアのドリフト方向を
示す。
FIG. 2 (a) shows a hole injection type device, and FIG. 2 (c)
FIG. 2 is a schematic view of a conventional structure of an electron injection element. (A),
Specific examples of (b) include InP / InGaAs-based APD and Ga, respectively.
As / GaAlAs Superlattice APD [Semiconductors and Semimetals Vol.22
p117 (1985) Academic Press Inc. (Academic Press Inc.). In the same figure, black circles (●) and white circles ()) indicate electrons and holes generated in the light absorption layer by light indicated by wavy lines, and arrows indicate the drift directions of the respective carriers in APD operation. .

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

素子の高速化,暗電流の低減のため、pn接合を用いる
通常のAPDでは、接合面積を限定し、小さくする必要が
ある。そのような観点から、第2図(a),(c)の構
造を比較すると、(a)では限定されたp型領域を持つ
プレーナ型、(c)ではメサ型である。素子の信頼性,
表面準位の影響を考慮するとPN接合露出部の少ないプレ
ーナ型が望ましい。
In order to increase the speed of the device and reduce the dark current, in a normal APD using a pn junction, the junction area needs to be limited and reduced. From such a viewpoint, comparing the structures of FIGS. 2 (a) and 2 (c), FIG. 2 (a) shows a planar type having a limited p-type region, and FIG. 2 (c) shows a mesa type. Element reliability,
In consideration of the influence of the surface state, a planar type having few PN junction exposed portions is desirable.

しかし、従来の構造では、電子注入型の(c)タイプ
では、プレーナ構造を簡単に作製することは、困難であ
る。
However, in the conventional structure, it is difficult to easily fabricate a planar structure with the electron injection type (c).

第2図(b)は、代表的な電子注入型のAPDであるSi
−APD構造の原理的構成を示した図であるが、この場合
には、n型不純物打込みによりプレーナ化が可能であ
る。しかし、光通信用APD材料であるIII−V族化合物半
導体では、n型不純物の選択拡散、あるいはイオン打込
みにより1〜2μmの深さをもつn型領域を作製するこ
とは、現状の作製プロセス技術では困難である。また、
他の作製方法として、(b)に相当する構造を多数回の
結晶成長で作製する方法も考えられるが、再成長界面の
結晶性の低下のため、実用素子に適用することは難し
い。
FIG. 2 (b) shows a typical electron injection type APD, Si.
FIG. 3 is a diagram showing a principle configuration of an APD structure. In this case, planarization can be achieved by implanting n-type impurities. However, in III-V compound semiconductors that are APD materials for optical communication, it is difficult to form an n-type region having a depth of 1 to 2 μm by selective diffusion of n-type impurities or ion implantation. Is difficult. Also,
As another manufacturing method, a method of manufacturing a structure corresponding to (b) by multiple crystal growths can be considered, but it is difficult to apply the structure to a practical device due to a decrease in crystallinity at a regrowth interface.

本発明の目的は、電子注入型のAPDにおいてプレーナ
化が可能な構造、および実用可能な素子の作製法を提案
することである。
An object of the present invention is to propose a structure that can be made planar in an electron injection type APD and a method for manufacturing a practicable element.

〔課題を解決するための手段〕[Means for solving the problem]

第2図(d)に本発明のAPDの模式図を示す。本発明
の構造は、同図(b)の構造と同様であり、同図(a)
の導電型を逆にした構造である。本構造により電子注入
条件が満たされることは明らかである。また、本構造が
増倍層に、k>1であることが知られているInGaAs/InA
lAs超格子増倍層を用いる。
FIG. 2 (d) shows a schematic diagram of the APD of the present invention. The structure of the present invention is the same as the structure shown in FIG.
Is a structure in which the conductivity type is reversed. It is clear that this structure satisfies the electron injection condition. In addition, the structure of this multiplication layer is InGaAs / InA, which is known to have k> 1.
An lAs superlattice multiplication layer is used.

本構造の作製方法としては、中央の受光機能部のpn接
合を含む多層構造を結晶成長により作製し、その後にZn
拡散,Beイオン打込み等によりp型接合制限領域を形成
すればよい。
As a method of manufacturing this structure, a multilayer structure including a pn junction of the central light receiving function portion is manufactured by crystal growth, and then Zn is formed.
The p-type junction limiting region may be formed by diffusion, Be ion implantation, or the like.

本発明において、第2図(d)は、基本原理図であ
り、後述の実施例に示す通り、他の層を付加すること、
増倍層等の導電型を変えることといつた変形が可能であ
る。
In the present invention, FIG. 2 (d) is a basic principle diagram, and as shown in an embodiment described later, adding another layer,
Deformation is possible by changing the conductivity type of the multiplication layer and the like.

〔作用〕[Action]

本発明の特長は、受光機能に関与する主要なpn接合部
の結晶表面への露出を防ぐことができることである。こ
のことは、電子注入型の従来例(第1図(c)と比較す
れば明らかである。その結果、表面リーク電流の減少,
素子の安定動作,信頼性の向上が可能となる。
A feature of the present invention is that it is possible to prevent the main pn junction involved in the light receiving function from being exposed to the crystal surface. This is clear from comparison with the conventional example of the electron injection type (FIG. 1 (c). As a result, a reduction in surface leakage current,
The stable operation of the element and the improvement of the reliability can be achieved.

〔実施例〕〔Example〕

実施例1 第1図(a)に本発明の一実施例の受光装置を示す。
本実施例は、イオン化率比k>1を満たすInGaAs/InAlA
s超格子26を増倍層とするプレーナ型APDである。p−In
P基板(p=2×1018cm-3)30上にp−InAlAsバツフア
層(p=2×1018cm-3、膜厚d=1μm)29、p−InGa
As光吸収層(p=5×1015cm-3,d=1.5μm)28、p−I
nAlAs電界緩和層(p=5×1016cm-3,d=0.2μm)27、
p−InGaAs/InAlAs超格子増倍層(p=1×1015cm-3,In
GaAsウエール層,幅15nm,InAlAsバリア層幅15nm,周期数
15)26、n−InAlAs層(n=2×1018cm-3,d=1μm)
25、およびn−InGaAsコンタクト層(n=1×1019c
m-3,d=0.2μm)24の6層を積層している。22はSiNパ
シベーシヨン膜、21,31は電極である。本発明の接合領
域を制限するためのp型領域は、23の斜線部である。
Embodiment 1 FIG. 1A shows a light receiving device according to an embodiment of the present invention.
In this embodiment, InGaAs / InAlA satisfying the ionization rate ratio k> 1
This is a planar APD having the s superlattice 26 as a multiplication layer. p-In
A p-InAlAs buffer layer (p = 2 × 10 18 cm −3 , film thickness d = 1 μm) 29 on a P substrate (p = 2 × 10 18 cm −3 ) 30, p-InGa
As light absorbing layer (p = 5 × 10 15 cm −3 , d = 1.5 μm) 28, p-I
nAlAs electric field relaxation layer (p = 5 × 10 16 cm −3 , d = 0.2 μm) 27,
p-InGaAs / InAlAs superlattice multiplication layer (p = 1 × 10 15 cm −3 , In
GaAs wale layer, width 15nm, InAlAs barrier layer width 15nm, cycle number
15) 26, n-InAlAs layer (n = 2 × 10 18 cm −3 , d = 1 μm)
25, and n-InGaAs contact layer (n = 1 × 10 19 c
m −3 , d = 0.2 μm) 24 are laminated. Reference numeral 22 denotes a SiN passivation film, and reference numerals 21 and 31 denote electrodes. The p-type region for limiting the junction region according to the present invention is indicated by 23 shaded portions.

素子の作製は、分子線エピタキシ法による結晶成長
(成長温度500℃),焼化亜鉛を用いた選択拡散,プラ
ズマCVDによるSiNパシベーシヨン膜形成,真空蒸着法に
よるn電極形成,リフトオフ法によるn電極パターニン
グ,電子ビーム蒸着法によるCr−Aup側電極形成を順次
行なつた。p領域23の深さは〜3μmとし、受光部pn接
合(25,26界面)より深くした。
The device is fabricated by crystal growth by molecular beam epitaxy (growth temperature 500 ° C), selective diffusion using zinc calcined, formation of SiN passivation film by plasma CVD, formation of n-electrode by vacuum deposition, and patterning of n-electrode by lift-off. Then, Cr-Aup side electrodes were formed sequentially by electron beam evaporation. The depth of the p region 23 was set to about 3 μm, and was made deeper than the pn junction (the interface between 25 and 26) of the light receiving portion.

第1図(b)は(a)と同様な構造,同様なプロセス
で作製したAPDであるが、p領域の深さを1.2μmとし、
受光部接合位置と一致させたものである。
FIG. 1B shows an APD manufactured by the same structure and the same process as that of FIG. 1A, except that the depth of the p region is 1.2 μm.
This is the same as the light receiving unit joining position.

第1図(a),(b)に示した素子の電気特性,光学
特性を評価した。その結果、最大増倍率は、(a),
(b)それぞれ30,25、増倍率1での暗電流は、それぞ
れ、100nA,40nA,利得・帯位積はそれぞれ95GHz,90GHzと
良好な結果を得た。なお、面内感度分布は、やや(a)
の方が良好であつた。
The electrical and optical characteristics of the devices shown in FIGS. 1A and 1B were evaluated. As a result, the maximum multiplication factor is (a),
(B) Good results were obtained at dark currents of 100 and 40 nA, respectively, with gains and band products of 95 GHz and 90 GHz, respectively, at 30, 25 and a gain of 1. Note that the in-plane sensitivity distribution is slightly (a)
Was better.

次に、第1図(a)のp領域23を除去した構造に相当
するメサ型素子を試作し、上記特性を比較した。メサ型
素子では、暗電流が800nAと大きく、本発明の改善効果
の1つと考えられる。なお、増倍率,帯域に関する特性
に顕著な差はみられなかつた。
Next, a mesa element corresponding to the structure in which the p region 23 in FIG. 1A was removed was prototyped, and the above characteristics were compared. The mesa-type device has a large dark current of 800 nA, which is considered to be one of the improvement effects of the present invention. It should be noted that there was no remarkable difference in the characteristics regarding the multiplication factor and the band.

次に本発明により予想される素子の信頼性,寿命の改
善効果を調べるため、前述の(a),(b)及びメサ型
の3ケの素子を逆方向電流100μA、周囲温度20℃の条
件で寿命試験を行なつた。本発明の実施例である第1図
(a),(b)の素子は共に106krに相当する時間まで
特性劣化は観測されなかつた。一方、メサ型素子では10
4krに相当する時間で暗電流の顕著な増大を示し、本発
明の効果が確認された。
Next, in order to examine the effects of improving the reliability and life expectancy of the device expected according to the present invention, the above three devices (a), (b) and the mesa type were subjected to a reverse current of 100 μA and an ambient temperature of 20 ° C. A life test was conducted. In each of the elements shown in FIGS. 1A and 1B according to the embodiment of the present invention, no characteristic deterioration was observed until a time corresponding to 10 6 kr. On the other hand, 10
At a time corresponding to 4 kr, a remarkable increase in dark current was observed, confirming the effect of the present invention.

続いて別の実施例を第1図(c)に示す。本素子は、
p−InGaAsを光吸収層48,n−InAlAsを増倍層46とするプ
レーナ型APDである。第1図(a)の実施例との違い
は、表面入射型であるため、受光部のInGaAsコンタクト
層44を除去したこと、増倍層46をn型InAlAs(n=1×
1015cm-3,d=1μm)としたこと、本発明のp領域43を
Beイオン打込みとそれに続くアニール処理により形成し
たことである。本素子も前述の寿命試験において106
間に相当する信頼性,特性安定性を示した。
Subsequently, another embodiment is shown in FIG. This element is
This is a planar APD having a light absorption layer 48 of p-InGaAs and a multiplication layer 46 of n-InAlAs. The difference from the embodiment of FIG. 1 (a) is that the InGaAs contact layer 44 of the light receiving section is removed and the multiplication layer 46 is replaced with n-type InAlAs (n = 1 ×
10 15 cm −3 , d = 1 μm).
It is formed by Be ion implantation and subsequent annealing. Reliability present element corresponding to 10 6 hours at life test described above, exhibited the characteristic stability.

〔発明の効果〕 本発明によれば、電子注入型のAPDでプレーナ構造を
容易に作製できる。その際、主接合を大気にさらす工程
を含まないため、プロセス起因の素子特性の劣化、特に
暗電流の増大を防ぐことができる。さらに、プレーナ化
することにより、動作特性の安定性,再現性を実現で
き、また素子の信頼性,寿命を向上できる。
[Effects of the Invention] According to the present invention, a planar structure can be easily manufactured using an electron injection type APD. At this time, since a step of exposing the main junction to the air is not included, deterioration of device characteristics due to a process, particularly an increase in dark current can be prevented. Further, by using a planar structure, stability and reproducibility of operating characteristics can be realized, and reliability and life of the element can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a),(b),(c)は本発明の実施例になる
APDの構造を示す断面図、第2図(a),(b),
(c)は従来構造のAPDの断面図、第2図(d)は本発
明の原理的構成を示すAPDの断面図である。 21,31,41,51……電極、23,43……p型領域、25,45……
n−InAlAs、26……n−InAlAs/InGaAs多重量子井戸増
倍層、27,47……p−InAlAs電界緩和層、28,48……p−
InGaAs光吸収層、46……p−InAlAs増倍層。
1 (a), 1 (b) and 1 (c) show an embodiment of the present invention.
Sectional views showing the structure of the APD, FIGS.
FIG. 2C is a cross-sectional view of an APD having a conventional structure, and FIG. 2D is a cross-sectional view of the APD showing a basic configuration of the present invention. 21,31,41,51 ... electrode, 23,43 ... p-type region, 25,45 ...
n-InAlAs, 26 ... n-InAlAs / InGaAs multiple quantum well multiplication layer, 27,47 ... p-InAlAs electric field relaxation layer, 28,48 ... p-
InGaAs light absorption layer, 46... P-InAlAs multiplication layer.

フロントページの続き (72)発明者 野津 千秋 千葉県茂原市早野3681番地 日立デバイ スエンジニアリング株式会社内 (72)発明者 大歳 創 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 石田 宏司 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (56)参考文献 特開 平1−205477(JP,A) 特開 昭63−128679(JP,A) 特開 昭60−58684(JP,A) 特開 昭60−49681(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 31/10Continued on the front page (72) Inventor Chiaki Notsu 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. 72) Inventor Koji Ishida 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-1-205477 (JP, A) JP-A-63-128679 (JP, A) JP-A-60-58684 (JP, A) JP-A-60-49681 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 31/10

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】所定の化合物半導体基板と、この化合物半
導体基板の上部に設けられた、入射光を受けてキャリア
を生成する光吸収層と、この生成された前記キャリアを
増倍する電子注入型増倍領域と、pn接合とを少なくとも
有する受光装置であって、前記光吸収領域はp型のIII
−V族化合物半導体で構成され、前記増倍領域は超格子
構造にて形成されておりp型の特性を示すと共にこの超
格子構造の電子とホールとに対するイオン化率αとβと
の比(k=α/β)が1より大きく、且つ前記pn接合は
前記化合物半導体基板の基板面に平行な方向では、n型
のIII−V族化合物半導体層に不純物拡散により導入
し、形成されたp型不純物領域に囲まれて存在し、前記
pn接合の前記化合物半導体基板の基板面に交叉する方向
では、前記光吸収領域および前記増倍領域に達せず、少
なくとも前記光吸収層および前記増倍領域が前記pn接合
と前記化合物半導体基板との間に存在し、且つ前記化合
物半導体基板側にn電極と、前記n型のIII−V族化合
物半導体層側にp電極とを有することを特徴とする受光
装置。
1. A predetermined compound semiconductor substrate, a light absorbing layer provided on the compound semiconductor substrate and receiving incident light to generate carriers, and an electron injection type for multiplying the generated carriers. A light receiving device having at least a multiplication region and a pn junction, wherein the light absorption region is a p-type III
The multiplication region is formed of a superlattice structure, exhibits p-type characteristics, and has a ratio (k) between the ionization rates α and β for electrons and holes in the superlattice structure. = Α / β) is greater than 1 and the pn junction is introduced into the n-type group III-V compound semiconductor layer by impurity diffusion in a direction parallel to the substrate surface of the compound semiconductor substrate to form a p-type junction. Exists between the impurity regions,
In the direction crossing the substrate surface of the compound semiconductor substrate of the pn junction, the light absorption region and the multiplication region do not reach the light absorption region and the multiplication region, and at least the light absorption layer and the multiplication region are formed between the pn junction and the compound semiconductor substrate. A light receiving device, which is located between the two and has an n-electrode on the compound semiconductor substrate side and a p-electrode on the n-type III-V compound semiconductor layer side.
JP1307724A 1989-11-29 1989-11-29 Light receiving device Expired - Fee Related JP2854634B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1307724A JP2854634B2 (en) 1989-11-29 1989-11-29 Light receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1307724A JP2854634B2 (en) 1989-11-29 1989-11-29 Light receiving device

Publications (2)

Publication Number Publication Date
JPH03169084A JPH03169084A (en) 1991-07-22
JP2854634B2 true JP2854634B2 (en) 1999-02-03

Family

ID=17972488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1307724A Expired - Fee Related JP2854634B2 (en) 1989-11-29 1989-11-29 Light receiving device

Country Status (1)

Country Link
JP (1) JP2854634B2 (en)

Also Published As

Publication number Publication date
JPH03169084A (en) 1991-07-22

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