EP0229948B1 - Circuit de transmission de données en série - Google Patents

Circuit de transmission de données en série Download PDF

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Publication number
EP0229948B1
EP0229948B1 EP19860116724 EP86116724A EP0229948B1 EP 0229948 B1 EP0229948 B1 EP 0229948B1 EP 19860116724 EP19860116724 EP 19860116724 EP 86116724 A EP86116724 A EP 86116724A EP 0229948 B1 EP0229948 B1 EP 0229948B1
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EP
European Patent Office
Prior art keywords
data
data transmission
circuit arrangement
transmission path
accordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19860116724
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German (de)
English (en)
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EP0229948A2 (fr
EP0229948A3 (en
Inventor
Hartmut Hantsch
Josef Mahalek
Peter Dr. Thoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bayerische Motoren Werke AG
Conti Temic Microelectronic GmbH
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Bayerische Motoren Werke AG
Temic Telefunken Microelectronic GmbH
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Publication of EP0229948A2 publication Critical patent/EP0229948A2/fr
Publication of EP0229948A3 publication Critical patent/EP0229948A3/de
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
    • G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
    • G08C15/12—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division the signals being represented by pulse characteristics in transmission link
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements

Definitions

  • the invention relates to an electronic circuit arrangement for serial data transmission with a transmitting device with a plurality of bit-parallel input information, a serial data transmission path and a receiving device, via which the transmitted data are converted into bit-parallel output information for controlling actuators or logistics circuits, the data to be transmitted being transmitted on the data transmission path form a data word, which is composed of a start pulse, several information units corresponding to the number of bit-parallel input information that form a data block, and a defined data pause.
  • a circuit arrangement is known in principle from DE-OS 34 10 082.
  • the transmission of data in time division multiplexing is known from telecommunications technical reports, "Fernwirktechnik V", volume 31, 1966, Verlag Vierweg, Braunschweig, page 6. From "Technical Bulletin No. 216" July 1973, pages 1 and 2, Koning en Hartmann, a data transmission path is known which has been expanded from 8 to 16 bit both on the send and on the receive side.
  • bit-parallel signals into bit-serial signals or the reversal of this process is a necessity in remote data processing or telex communication.
  • local computer network networks also make use of this conversion if, for example, a terminal is installed in a different building wing than the computer
  • microprocessors separate peripheral components, so-called universal synchronous / asynchronous receivers / transmitters (USART), can be used for this conversion.
  • USBART universal synchronous / asynchronous receivers / transmitters
  • software solutions are also known in which standard I / O ports can be used.
  • the data to be transmitted are defined by the ASCII code (American Standard Code for Information Interchange) and the levels on the transmission lines are standardized in special standards such as the RS 232 voltage interface (CCITT recommendation from V24).
  • ASCII code American Standard Code for Information Interchange
  • CITT recommendation from V24 the RS 232 voltage interface
  • a microprocessor solution for serial data transmission is too complex if, for example, switch positions for different consumers are to be converted into a serial data word as parallel input information in order to control bit-parallel relays as actuators on the receiver side in accordance with the switch positions .
  • bit-parallel input information is expanded via the I / O ports with appropriate addressing and software programming.
  • the present invention has for its object to provide a circuit arrangement for converting bit-parallel to bit-serial data and vice versa, which requires little circuitry and does not require software, and that the number of bit-parallel input or output information can be changed if necessary.
  • the circuit arrangement according to the invention has the essential advantage that many control outputs of a wiring harness can be saved with regard to the motor vehicle electronics without programming effort and by means of similar transmission and reception devices, the data transmission security is increased by multiple comparisons and an interruption of the data transmission path can be diagnosed.
  • the block diagram shown in Figure 1 is composed of several similar transmission devices S o , S1, ... S n , a data transmission link Ü and several receiving devices E o , E1 ... E n .
  • Each transmission device S n has an equal number of parallel input information I En , in the example shown there are eight, which, according to the arrangement of the n transmission devices S n, are sequentially combined on the data transmission path U to form a data word, as shown in FIG. 2.
  • the input information I En is converted into the same number of corresponding parallel output information I An in the assigned receiving devices E n in order to control relays as final control elements (St) or directly logic circuits.
  • the data word in FIG. 2 consists of a start pulse SI with a pulse duration of, for example, 312 ⁇ s, followed by several data blocks DB corresponding to the number of bit-parallel input information, followed by a defined data pause DP.
  • a data block consists of a synchronization bit with, for example, 156 microseconds, a subsequent information bit of the same duration, followed by two zero bits each of 156 microseconds duration.
  • the transmitting device S is constructed as shown in FIG. 3: Via an oscillator OSZ, which can be influenced in its basic frequency by external circuitry at connection 0, a clock frequency f o is generated, which is fed via the one input of a first OR gate OR 1 to a frequency divider stage T.
  • the other input of the OR gate OR 1 can be supplied with an external clock generator via the clock input terminal TE, in particular when several identical transmission devices S n are cascaded and by only one transmission device, the master - for example S o - the clock for all downstream transmission devices S n is derived.
  • the oscillator inputs O n of these downstream transmission devices are connected to low potential, and they then work as so-called slaves in cooperation with the master.
  • the frequency divider stage T consists of a chain of feedback bistable flip-flops, for example D flip-flops, so that different frequency divider ratios are present, and the divided frequency positions are used to form the data word via decoding circuits according to the invention, such as start pulse decoder SID, cascade rest decoder KD, pulse-pause decoder PPD, release decoder FD and scan-pulse decoder SCD linked together, in addition the frequency divider stage T controls a delay circuit VZ.
  • the pulse scheme shown in Figure 6 shows the output signals of the individual decoding circuits.
  • Each scan pulse SCI n of the scan pulse decoder SCD is fed to the base of an associated transistor T n in FIG. 3, the emitter of which is connected to the interface of the input information circuit.
  • the connection pin for this input information I En is also connected to reference potential via a reverse zener diode.
  • the collectors of all transistors T n are connected together and fed to the inverting input of a comparator K7. This input is also connected via a resistor R 1 to an operating voltage supply unit U stab / POR.
  • the same operating voltage supply unit feeds a voltage divider from the two resistors R2, R3, the connection node of which is fed to the non-inverting input of the comparator stage K7.
  • the output signals from the comparator stage K7 and release decoder FD are linked via an AND gate AND1, the output signal of which is fed to an input of a second OR gate OR2 with several inputs.
  • the output signals of the start pulse decoder SID and the pulse pause decoder PPD are fed to the further inputs of this OR gate.
  • Via an amplifier V 1 with the connection data input slave DES the data of the downstream transmission device, for example S 1, which is operated as a slave, is fed to a further input of the OR gate OR 2, the output of which drives a push-pull output stage GT, the output signal of which drives the data word on the Data transmission path represents U.
  • the push-pull output stage GT is blocked for sending a data word W immediately after the supply voltage U s is applied via the output of the delay circuit VZ for a defined period of time, which is determined by counting a specific frequency position of the divider stage T.
  • the output signal of the cascade reset decoder KD is fed via a second amplifier circuit V2 to the connection for the cascade reset output KRA.
  • the signal of the fundamental frequency f o is present at the connection of the clock output TA via a third amplifier V3.
  • the supply voltage supply unit U stab / POR is supplied with a supply voltage U s , from which the stabilized voltage U stab is derived.
  • the data word W shown in FIG. 6p begins with a start pulse of, for example, 312 microseconds in duration, followed by eight data blocks DB each with a duration of 624 microseconds, each data block starting with a synchronization bit of 156 microseconds in duration. It is followed by the scanned input information I En , with a logical 0 meaning that the switch in question is closed. In the example in FIG. 6p, every second switch is closed. The information bit is followed by two zero bits of 156 ⁇ s each.
  • the frequency divider stages T and the pulse-pause decoder PPD can be blocked at their cascade reset input KRE at a logic zero level and released at a high level.
  • the switching of these levels is carried out in cascading operation in master-slave mode by the cascade reset signal, which is generated in the cascade reset decoder KD and is available at the cascade reset output KRA of the master, and the slave-operated downstream transmission device is supplied.
  • a galvanically coupled electrical connecting line can be used as the data transmission path Ü.
  • it is also an optoelectronic transmission line possible, which consists, for example, of a light-emitting diode LED on the transmitter side, which is driven by the push-pull output stage GT with the connection DA of the data output of the transmission device.
  • This light-emitting diode pulses the data word W in an electrically isolated manner, for example via a glass fiber, to a phototransistor, which is arranged on the receiver side and controls the downstream receiving device.
  • the data input DE of the receiving device E is connected to the inverting input of a comparator stage K6 and to the cathode of a reverse polarized Zener diode Z2, the anode of which is connected to the reference potential.
  • the non-inverting input of this comparator is connected to a reference voltage via the center tap of a voltage divider consisting of resistors R5, R6.
  • the comparator K W receives the received data word W for further processing in the receiving device E digitally to a defined voltage level and supplies it with a start pulse detection circuit STE, a scanning pulse generator stage AP and an input of an AND gate AND2.
  • the AND gate AND2 is then released when the start pulse was detected in the start pulse detection circuit STE and the other input of the AND gate AND2 is driven with this signal.
  • the start pulse detection circuit is based on a divided frequency position of a frequency divider stage of the receiving device T E is controlled, in which after the end of the data pause the first negative edge is checked by counting to determine whether there is a minimum pulse duration that can be interpreted as a start pulse.
  • the frequency divider stage T E is used for this purpose by an oscillator circuit OSZ E controlled with the connection O E of the receiving device, whose fundamental frequency position f oE is approximately 4 times as large as that of the transmitting device.
  • the oscillator OSZ E can be blocked or enabled via the output of an operating mode memory BA by setting its connection, the programming pin PP, to high or low potential.
  • the basic frequency f oE of the oscillator OSZ E is additionally fed to a clock output stage TA with the connection TA E , the function of which is also determined by a corresponding control signal from the operating mode memory BA.
  • the frequency divider stage T E controls further modules of the receiving device E with differently divided frequency positions. These include the scanning pulse generator stage AP, a data end decoder DED, which recognizes the end of the transmitted data and communicates this point in time to a sequence control A.
  • the sequence control A is also controlled by different frequency positions of the divider stage T E.
  • the further processing of the received data word takes place via a first counting device Z 1, which is controlled via a further output signal of the operating mode memory BA and accordingly counts out the first eight bits as the master receiver or the second eight bits as the slave receiver.
  • the counter Z1 the output signal of the AND gate AND2 is supplied.
  • the output of the counter Z 1 and the output of the strobe generator stage AP control a data decoding circuit DD, the control lines of which assume a distribution function by being connected to a downstream buffer memory SPA, which consists of clock-controlled D flip-flops, at the clock inputs thereof. At all data inputs of these D flip-flops, the output signal of the AND gate AND2 is present, which is identical to the data word. As a result, only the input information I En is read into the flip-flops of the buffer memory SPA one after the other in the raster of the scanning pulse and is thus available as bit-parallel information.
  • the buffer SPA is followed by an identical buffer SPZ.
  • the information read into the buffer memory SPA is compared with the content of the intermediate memory SPZ after the end of the data has been recognized.
  • a second counter Z2 which works as a 4-way counter, is incremented.
  • the comparison of the data contents of the buffer memory SPA and the intermediate memory SPZ takes place in the comparator stage K 1, which emits a control signal to the counter Z 2 and the sequential control system in the event of equivalence.
  • the counter Z2 is reset via the sequence control A. This also controls the memory SPA, SPZ and SPO and the comparators K1 and K2. After each comparison, the data is transferred from the SPA buffer to the buffer. After four equivalents, the content of the intermediate memory SPZ is compared with the content of the output memory SPO connected to it via a comparator K2. At equivalence, the counter Z2 is reset because the input information I En have not changed.
  • the information is transferred from the buffer SPZ to the output memory SPO and transferred to the driver stages downstream of the output memory SPO, where it is available as bit-parallel output information I An for controlling actuators or logic circuits stand.
  • An output of the comparator K2 and a control line of the sequence control are fed to a short-circuit detection circuit KS, through which after approximately 35 ms after the data output from the output memory on the driver stages these are checked for short-circuit behavior for approximately 10 ms.
  • the collector-emitter voltages of the active driver stages which are designed as open-collector transistors with the connections TRA or I An , are queried four times in succession via a comparator stage to ensure that there is no interference pulse. If a short-circuit signal is present for approx. 10 ms, the corresponding transistor is blocked. The blocked state remains stored and can only be deleted by switching off and switching on the supply voltage supply unit U stab / POR again by a so-called "Power On Reset", which is carried out in the same way as that of the transmitting device.
  • a further protective measure for the driver stages is carried out by a safety test device PR, which is controlled by a frequency position of the frequency divider stage T E. This ensures that all driver outputs are blocked after a defined time of approx. 50 ms in the event of a break or short circuit in the data transmission path Ü.
  • the fault can be indicated optically or acoustically when input information from the transmitter device is fixed at a logic low level with reference potential and the corresponding output is wired according to FIG.
  • modules of the receiver circuit are three comparators K3, K4, K5, whose output signals act on the driver stages.
  • relays are controlled by the output stages, they can be statically controlled for approx. 120 ms after switching on. The short-circuit test of the outputs also takes place during this time. The outputs can then be driven in a clocked manner, with the fundamental frequency of the oscillator of the receiver circuit f oE , in order to reduce the power loss in the driver stages.
  • the operating mode for static or clocked activation of the outputs can be determined by the connection pin T Aus with the non-inverting input of the comparator K5, and the activation takes place statically when T Aus is connected to the supply voltage U s . Connection with reference potential leads to clocked activation.
  • the non-inverting inputs of the comparators K4 and K3 are connected to each other and led out to the connection LD.
  • the output of the comparator K4 is connected to the output of the comparator K5.
  • the input LD senses the voltage of the vehicle electrical system.
  • the driver transistors of the driver stages are switched to the conductive state via the output of the comparator K3, at the inverting input of which the reference voltage U Ref2 is located.
  • positive Overvoltages prevented any short-circuit interrogation.
  • the oscillator OSZ E at pin O E is wired with a RC member and the clock output TA E is active. If the receiver is operated alone, TA E is blocked.
  • the oscillator In the slave mode, the oscillator is locked and must be controlled by the master's clock output, the slave's clock output is locked.
  • the master recognizes the start bit and decodes the first 8 information bits.
  • the slave also recognizes the start bit, but decodes the second 8 information bits.
  • FIG. 5 shows a type of connection of the transmission device S o .
  • the supply voltage is supplied to the transmitting device via the data transmission link Ü.
  • the resistor R p in Figure 1 is replaced by the diode D p , the cathode with the Connection pin U S of the transmitter device S o and the anode are connected directly to the data transmission path Ü.
  • circuit blocks shown in FIGS. 3 and 4 can be integrated completely monolithically.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Error Detection And Correction (AREA)

Claims (12)

  1. Circuit pour la transmission sérielle de données, comprenant un dispositif d'émission (S) présentant plusieurs informations d'entrée (IEn) en parallèle par bit, une voie de transmission sérielle de données (Ü) et un dispositif de réception (E) par lequel les données transmises sont converties de façon appropriée en informations de sortie (IAn) en parallèle par bit pour la commande d'organes d'actionnement (St) ou de circuits logiques, les données à transmettre formant sur la voie de transmission (Ü) un mot de données (W) qui se compose d'une impulsion de départ (SI), plusieurs unités d'information correspondant au nombre des informations d'entrée en parallèle par bit, qui constituent un bloc de données (DB), ainsi que d'une pause ou absence de données (DP) définie, caractérisé en ce que le nombre des informations d'entrée et de sortie (IEn, Ian) en parallèle par bit est accru par la mise en cascade de plusieurs dispositifs d'émission ou de réception (Sn, En) de même type, dans une disposition selon laquelle, avec une commande rythmée synchrone, un dispositif d'émission et un dispositif de réception (So, Eo) servent chaque fois d'étage mâitre et les autres dispositifs d'émission et de réception servent d'étages esclaves, à l'aide d'un étage de programmation maître-esclave (MS) incorporé, de telle sorte que sur la voie de transmission de données (Ü), le mot de données (W) est changé par assemblage séquentiel d'un nombre accru correspondant de blocs de données (DB) avec chaque fois le même nombre d'unités d'information par bloc de données (DB), la sûreté de transmission des données étant accrue par des mémoires (SPA, SPZ, SPO) pour la comparaison multiple.
  2. Circuit selon la revendication 1, caractérisé en ce que, par la mise en cascade de plusieurs dispositifs d'émission ou de réception de même type, la génération du mot de données (W) sur la voie de transmission de données (Ü) provoque un raccourcissement de l'absence de données ou un prolongement du mot de données, ou encore une augmentation de la fréquence d'émission, et la juxtaposition séquentielle des blocs de données s'effectue dans le dispositif d'émission (S) à l'aide d'un circuit de mise en cascade (KD) et d'un dispositif de mémorisation (MS) programmable de l'extérieur, ce qui fixe l'ordre de succesion des différents blocs de données sur la voie de transmission de données (Ü) ainsi que, du côté des dispositifs de réception (E), la coordination des différents blocs de données aux dispositifs de réception (En) correspondants à l'aide d'un dispositif de mémorisation (BA) programmable en conséquence pour le mode de fonctionnement choisi.
  3. Circuit selon la revendication 1 ou 2, caractérisé en ce que la délivrance des données par le dispositif d'émission (S) sur la voie de transmission de données (Ü) s'effectue à travers un étage final symétrique (GT) comportant une limitation de courant.
  4. Circuit selon une des revendications précédentes, caractérisé en ce que, dans le dispositif de réception (E), à l'aide d'une commande séquentielle (A), d'une mémoire collectrice (SPA), d'une mémoire intermédiaire (SPZ) prévue à la suite et qui est elle-même suivie d'une mémoire de sortie (SPO), d'un premier comparateur (K₁) qui compare le contenu de la mémoire collectrice (SPA) avec le contenu de la mémoire intermédiaire (SPZ) et d'un deuxième comparateur (K₂) qui compare le contenu de la mémoire intermédiaire (SPZ) avec le contenu de la mémoire de sortie (SPO), ainsi que d'un compteur (Z₂), la sûreté de transmission du dispositif d'émission (S) et de la voie de transmission de données (Ü) à l'égard d'influences perturbatrices est accrue par l'interrogation à plusieurs reprises des mêmes informations d'entrée (IEn) et la comparaison consécutive de la configuration binaire reçue dans les comparateurs (K₁, K₂), suivie d'une incrémentation du compteur (Z₂) en cas d'équivalence, jusqu'à ce que soit obtenu un nombre prescrit défini, ou par la remise à zéro du compteur (Z₂) en cas de non-équivalence et nouvelle interrogation des informations d'entrée (IEn).
  5. Circuit selon une des revendications précédentes, caractérisé en ce que, en cas de court-circuit ou de rupture de la voie de transmission de données (Ü), tous les étages d'attaque (Tr) des sorties en parallèle par bit du dispositif de réception (E) sont bloqués après un temps de réponse défini.
  6. Circuit selon une des revendications précédentes, caractérisé en ce que la voie de transmission de données (Ü) est formée par une ligne de liaison électrique ou par un dispositif d'émission optoélectronique côté émetteur, une fibre de verre et une unité de réception optoélectronique côté recepteur.
  7. Circuit selon une des revendications précédentes, caractérisé en ce qu'une interruption de la voie de transmission de données (Ü) est affichée optiquement par une diode électroluminescente (DK) ou signalée acoustiquement par une unité de transduction électroacoustique, du fait que l'une des informations d'entrée (IEn) en parallèle par bit reste constamment ajustée au potentiel de référence et que la diode électroluminescente ou l'unité de transduction électroacoustique est connectée dans l'étage coordonné d'attaque en parallèle par bit.
  8. Circuit selon une des revendications précédentes, caractérisé en ce que la fourniture de la tension d'alimentation au dispositif d'émission s'effectue séparément ou à travers de la voie de transmission de données (Ü).
  9. Circuit selon une des revendications précédentes, caractérise en ce que les étages d'attaque (Tr) en parallèle par bit du dispositif de réception (E) sont commutés à l'état conducteur si la tension d'alimentation présente des pointes de tension élevées nuisibles.
  10. Circuit selon une des revendications précédentes, caractérisé en ce que, en cas de commande de relais en tant que consommateurs finaux, les unités d'information de sortie (IAn), en parallèle par bit, sont commandées, au choix, statiquement ou de façon rythmée afin de réduire la puissance dissipée à un minimum.
  11. Circuit selon une des revendications précédentes, caractérisé en ce que les étages d'attaque en parallèle par bit du dispositif de réception (E) sont contrôlés sur l'existence éventuelle d'un comportement de court-circuit de la charge raccordée par des interrogations successives des tensions collecteur-émetteur, le contrôle s'effectuant dans une trame ou fenêtre temporelle dans laquelle les étages d'attaque (Tr) du dispositif de réception (E) sont commutés à l'état conducteur.
  12. Circuit selon une des revendications précédentes, caractérisé par son utilisation dans l'électronique pour véhicules automobiles.
EP19860116724 1985-12-20 1986-12-02 Circuit de transmission de données en série Expired - Lifetime EP0229948B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3545293 1985-12-20
DE19853545293 DE3545293A1 (de) 1985-12-20 1985-12-20 Schaltungsanordnung zur seriellen datenuebertragung

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EP0229948A2 EP0229948A2 (fr) 1987-07-29
EP0229948A3 EP0229948A3 (en) 1989-04-26
EP0229948B1 true EP0229948B1 (fr) 1993-03-17

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EP (1) EP0229948B1 (fr)
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Also Published As

Publication number Publication date
JPH0771087B2 (ja) 1995-07-31
DE3545293A1 (de) 1987-07-02
EP0229948A2 (fr) 1987-07-29
JPS62159548A (ja) 1987-07-15
DE3688060D1 (de) 1993-04-22
US5067076A (en) 1991-11-19
EP0229948A3 (en) 1989-04-26
DE3545293C2 (fr) 1989-01-05

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