EP0229948B1 - Circuit for serial data transmission - Google Patents

Description

The invention relates to an electronic circuit arrangement for serial data transmission with a transmitting device with a plurality of bit-parallel input information, a serial data transmission path and a receiving device, via which the transmitted data are converted into bit-parallel output information for controlling actuators or logistics circuits, the data to be transmitted being transmitted on the data transmission path form a data word, which is composed of a start pulse, several information units corresponding to the number of bit-parallel input information that form a data block, and a defined data pause. Such a circuit arrangement is known in principle from DE-OS 34 10 082. Furthermore, the transmission of data in time division multiplexing is known from telecommunications technical reports, "Fernwirktechnik V", volume 31, 1966, Verlag Vierweg, Braunschweig, page 6. From "Technical Bulletin No. 216" July 1973, pages 1 and 2, Koning en Hartmann, a data transmission path is known which has been expanded from 8 to 16 bit both on the send and on the receive side.

The conversion of bit-parallel signals into bit-serial signals or the reversal of this process is a necessity in remote data processing or telex communication. However, local computer network networks also make use of this conversion if, for example, a terminal is installed in a different building wing than the computer With microprocessors, separate peripheral components, so-called universal synchronous / asynchronous receivers / transmitters (USART), can be used for this conversion. However, software solutions are also known in which standard I / O ports can be used.

For the transmission of teletype signals, for example, the data to be transmitted are defined by the ASCII code (American Standard Code for Information Interchange) and the levels on the transmission lines are standardized in special standards such as the RS 232 voltage interface (CCITT recommendation from V24).

For certain applications, such as in automotive electronics, a microprocessor solution for serial data transmission is too complex if, for example, switch positions for different consumers are to be converted into a serial data word as parallel input information in order to control bit-parallel relays as actuators on the receiver side in accordance with the switch positions .

In microprocessors, the bit-parallel input information is expanded via the I / O ports with appropriate addressing and software programming.

The present invention has for its object to provide a circuit arrangement for converting bit-parallel to bit-serial data and vice versa, which requires little circuitry and does not require software, and that the number of bit-parallel input or output information can be changed if necessary.

This object is achieved by the features of claim 1.

Advantages:
The circuit arrangement according to the invention has the essential advantage that many control outputs of a wiring harness can be saved with regard to the motor vehicle electronics without programming effort and by means of similar transmission and reception devices, the data transmission security is increased by multiple comparisons and an interruption of the data transmission path can be diagnosed.

Further advantageous embodiments of the invention result from the subclaims.

An embodiment of the invention is shown in the figures and is described in more detail below:

Figur 1:

Ein Blockschaltbild mehrerer kaskadierter Sende- bzw. Empfangseinrichtungen zur seriellen Datenübertragung.

Figur 2:

Den zeitlichen Verlauf eines Datenwortes.

Figur 3:

Ein Blockschaltbild der Sendeeinrichtung.

Figur 4:

Ein Blockschaltbild der Empfangseinrichtung.

Figur 5:

Eine Schaltungsanordnung zur Speisespannungsversorgung der Sendeeinrichtung über die Datenübertragungsstrecke.

Figur 6:

Ein Impulsschema für die Decodierschaltungen.

Figur 7:

Beschaltung der Empfangseinrichtung.

Show it:

Figure 1:

A block diagram of several cascaded transmitters and receivers for serial data transmission.

Figure 2:

The time course of a data word.

Figure 3:

A block diagram of the transmitter.

Figure 4:

A block diagram of the receiving device.

Figure 5:

A circuit arrangement for supplying power to the transmission device via the data transmission path.

Figure 6:

A pulse scheme for the decoding circuits.

Figure 7:

Wiring the receiving device.

The block diagram shown in Figure 1 is composed of several similar transmission devices S _o , S₁, ... S _n , a data transmission link Ü and several receiving devices E _o , E₁ ... E _n .

Each transmission device S _n has an equal number of parallel input information I _En , in the example shown there are eight, which, according to the arrangement of the n transmission devices S _{n, are} sequentially combined on the data transmission path U to form a data word, as shown in FIG. 2. On the receiver side, the input information I _{En is converted} into the same number of corresponding parallel output information I _An in the assigned receiving devices E _n in order to control relays as final control elements (St) or directly logic circuits.

The data word in FIG. 2 consists of a start pulse SI with a pulse duration of, for example, 312 μs, followed by several data blocks DB corresponding to the number of bit-parallel input information, followed by a defined data pause DP.

A data block consists of a synchronization bit with, for example, 156 microseconds, a subsequent information bit of the same duration, followed by two zero bits each of 156 microseconds duration.

For this purpose, the transmitting device S is constructed as shown in FIG. 3:
Via an oscillator OSZ, which can be influenced in its basic frequency by external circuitry at connection 0, a clock frequency f _{o is} generated, which is fed via the one input of a first OR gate OR 1 to a frequency divider stage T. The other input of the OR gate OR 1 can be supplied with an external clock generator via the clock input terminal TE, in particular when several identical transmission devices S _{n are} cascaded and by only one transmission device, the master - for example S _o - the clock for all downstream transmission devices S _{n is} derived. For this purpose, the oscillator inputs O _{n of} these downstream transmission devices are connected to low potential, and they then work as so-called slaves in cooperation with the master.

The following explanations relate to an exemplary embodiment of the invention with two identical transmitting and receiving devices.

The frequency divider stage T consists of a chain of feedback bistable flip-flops, for example D flip-flops, so that different frequency divider ratios are present, and the divided frequency positions are used to form the data word via decoding circuits according to the invention, such as start pulse decoder SID, cascade rest decoder KD, pulse-pause decoder PPD, release decoder FD and scan-pulse decoder SCD linked together, in addition the frequency divider stage T controls a delay circuit VZ.

The pulse scheme shown in Figure 6 shows the output signals of the individual decoding circuits.

• Scan-Impulse für die Abfrage der Schalterstellungen gemaß Figur 6b bis 6i.
• Puls-Pausendecoder-Impuls gemäß Figur 6l.
• Startimpuls gemäß Figur 6k.
• Die Eingangsinformationen gemäß Figur 6m an einem Beispiel dargestellt.
• Freigabeimpulse gemäß Figur 6n.
• Die zwischengespeicherten Eingangsinformationen gemäß Figur 6o.
• Das eigentliche Datenwort wie es auf der Datenübertragungsstrecke ausgesendet wird, gemäß Figur 6p.
• Das Ausgangssignal des Kaskade-Reset-Decoders gemäß Figur 6q.

The following output signals are generated from the clock frequency f _{o of} the oscillator output signal according to FIG. 6a via the decoding circuits:

• Scan pulses for querying the switch positions according to Figure 6b to 6i.
• Pulse pause decoder pulse according to Figure 6l.
• Start pulse according to Figure 6k.
• The input information according to FIG. 6m is shown using an example.
• Release pulses according to Figure 6n.
• The temporarily stored input information according to FIG. 6o.
• The actual data word as it is sent out on the data transmission link, according to FIG. 6p.
• The output signal of the cascade reset decoder according to Figure 6q.

The interaction of the individual decoded pulses takes place as follows:

Each scan pulse SCI _{n of} the scan pulse decoder SCD is fed to the base of an associated transistor T _n in FIG. 3, the emitter of which is connected to the interface of the input information circuit. The connection pin for this input information I _En is also connected to reference potential via a reverse zener diode. The collectors of all transistors T _n are connected together and fed to the inverting input of a comparator K₇. This input is also connected via a resistor R 1 to an operating voltage _{supply unit} U _stab / POR.

The same operating voltage supply unit feeds a voltage divider from the two resistors R₂, R₃, the connection node of which is fed to the non-inverting input of the comparator stage K₇.

Shows the input information I _En at the time of the pending scan pulse SCI _n a logic high level greater than 2.5 V, for example, this state is interpreted as an open switch and the output signal of the comparator K 1 is logic zero or low potential. Conversely, if the input information is logic zero or is at low level, that is, the switch is closed, the output signal of the comparator K₁ is logic 1 or high level.

The output signals from the comparator stage K₇ and release decoder FD are linked via an AND gate AND₁, the output signal of which is fed to an input of a second OR gate OR₂ with several inputs. The output signals of the start pulse decoder SID and the pulse pause decoder PPD are fed to the further inputs of this OR gate. Via an amplifier V 1 with the connection data input slave DES, the data of the downstream transmission device, for example S 1, which is operated as a slave, is fed to a further input of the OR gate OR 2, the output of which drives a push-pull output stage GT, the output signal of which drives the data word on the Data transmission path represents U.
The push-pull output stage GT is blocked for sending a data word W immediately after the supply voltage U _{s is applied} via the output of the delay circuit VZ for a defined period of time, which is determined by counting a specific frequency position of the divider stage T.

The output signal of the cascade reset decoder KD is fed via a second amplifier circuit V₂ to the connection for the cascade reset output KRA.

The signal of the fundamental frequency f _{o is present} at the connection of the clock output TA via a third amplifier V₃.

The supply voltage supply unit U _stab / POR is supplied with a supply voltage U _s , from which the stabilized voltage U _{stab is} derived.

The data word W shown in FIG. 6p begins with a start pulse of, for example, 312 microseconds in duration, followed by eight data blocks DB each with a duration of 624 microseconds, each data block starting with a synchronization bit of 156 microseconds in duration. It is followed by the scanned input information I _En , with a logical 0 meaning that the switch in question is closed. In the example in FIG. 6p, every second switch is closed. The information bit is followed by two zero bits of 156 µs each.

Via the master-slave programming stage MS, the frequency divider stages T and the pulse-pause decoder PPD can be blocked at their cascade reset input KRE at a logic zero level and released at a high level. The switching of these levels is carried out in cascading operation in master-slave mode by the cascade reset signal, which is generated in the cascade reset decoder KD and is available at the cascade reset output KRA of the master, and the slave-operated downstream transmission device is supplied.

A galvanically coupled electrical connecting line can be used as the data transmission path Ü. But it is also an optoelectronic transmission line possible, which consists, for example, of a light-emitting diode LED on the transmitter side, which is driven by the push-pull output stage GT with the connection DA of the data output of the transmission device.
This light-emitting diode pulses the data word W in an electrically isolated manner, for example via a glass fiber, to a phototransistor, which is arranged on the receiver side and controls the downstream receiving device.

The data input DE of the receiving device E is connected to the inverting input of a comparator stage K₆ and to the cathode of a reverse polarized Zener diode Z₂, the anode of which is connected to the reference potential.
The non-inverting input of this comparator is connected to a reference voltage via the center tap of a voltage divider consisting of resistors R5, R6.

The comparator K W receives the received data word W for further processing in the receiving device E digitally to a defined voltage level and supplies it with a start pulse detection circuit STE, a scanning pulse generator stage AP and an input of an AND gate AND₂. The AND gate AND₂ is then released when the start pulse was detected in the start pulse detection circuit STE and the other input of the AND gate AND₂ is driven with this signal. The start pulse detection circuit is based on a divided frequency position of a frequency divider stage of the receiving device T _{E is} controlled, in which after the end of the data pause the first negative edge is checked by counting to determine whether there is a minimum pulse duration that can be interpreted as a start pulse. The frequency divider stage T _E is used for this purpose by an oscillator circuit OSZ _E controlled with the connection O _{E of} the receiving device, whose fundamental frequency position f _{oE is} approximately 4 times as large as that of the transmitting device. The oscillator OSZ _E can be blocked or enabled via the output of an operating mode memory BA by setting its connection, the programming pin PP, to high or low potential.

The basic frequency f _{oE of} the oscillator OSZ _E is additionally fed to a clock output stage TA with the connection TA _E , the function of which is also determined by a corresponding control signal from the operating mode memory BA.

The frequency divider stage T _E controls further modules of the receiving device E with differently divided frequency positions. These include the scanning pulse generator stage AP, a data end decoder DED, which recognizes the end of the transmitted data and communicates this point in time to a sequence control A.
The sequence control A is also controlled by different frequency positions of the divider stage T _E. The further processing of the received data word takes place via a first counting device Z 1, which is controlled via a further output signal of the operating mode memory BA and accordingly counts out the first eight bits as the master receiver or the second eight bits as the slave receiver. In addition, the counter Z₁ the output signal of the AND gate AND₂ is supplied.

The output of the counter Z 1 and the output of the strobe generator stage AP control a data decoding circuit DD, the control lines of which assume a distribution function by being connected to a downstream buffer memory SPA, which consists of clock-controlled D flip-flops, at the clock inputs thereof. At all data inputs of these D flip-flops, the output signal of the AND gate AND₂ is present, which is identical to the data word. As a result, only the input information I _{En is} read into the flip-flops of the buffer memory SPA one after the other in the raster of the scanning pulse and is thus available as bit-parallel information. The buffer SPA is followed by an identical buffer SPZ.

The information read into the buffer memory SPA is compared with the content of the intermediate memory SPZ after the end of the data has been recognized. With equivalence, a second counter Z₂, which works as a 4-way counter, is incremented. The comparison of the data contents of the buffer memory SPA and the intermediate memory SPZ takes place in the comparator stage K 1, which emits a control signal to the counter Z 2 and the sequential control system in the event of equivalence.

In the event of antivalence, the counter Z₂ is reset via the sequence control A. This also controls the memory SPA, SPZ and SPO and the comparators K₁ and K₂. After each comparison, the data is transferred from the SPA buffer to the buffer. After four equivalents, the content of the intermediate memory SPZ is compared with the content of the output memory SPO connected to it via a comparator K₂. At equivalence, the counter Z₂ is reset because the input information I _{En have} not changed. In the event of non-equivalence, the input information has changed and the following process takes place: The information is transferred from the buffer SPZ to the output memory SPO and transferred to the driver stages downstream of the output memory SPO, where it is available as bit-parallel output information I _An for controlling actuators or logic circuits stand.

An output of the comparator K₂ and a control line of the sequence control are fed to a short-circuit detection circuit KS, through which after approximately 35 ms after the data output from the output memory on the driver stages these are checked for short-circuit behavior for approximately 10 ms. For this purpose, the collector-emitter voltages of the active driver stages, which are designed as open-collector transistors with the connections TRA or I _An , are queried four times in succession via a comparator stage to ensure that there is no interference pulse.
If a short-circuit signal is present for approx. 10 ms, the corresponding transistor is blocked.
The blocked state remains stored and can only be deleted by switching off and switching on the supply voltage supply unit U _stab / POR again by a so-called "Power On Reset", which is carried out in the same way as that of the transmitting device.

A further protective measure for the driver stages is carried out by a safety test device PR, which is controlled by a frequency position of the frequency divider stage T _E.
This ensures that all driver outputs are blocked after a defined time of approx. 50 ms in the event of a break or short circuit in the data transmission path Ü. The fault can be indicated optically or acoustically when input information from the transmitter device is fixed at a logic low level with reference potential and the corresponding output is wired according to FIG.

Other modules of the receiver circuit are three comparators K₃, K₄, K₅, whose output signals act on the driver stages.

If, for example, relays are controlled by the output stages, they can be statically controlled for approx. 120 ms after switching on. The short-circuit test of the outputs also takes place during this time. The outputs can then be driven in a clocked manner, with the fundamental frequency of the oscillator of the receiver circuit f _oE , in order to reduce the power loss in the driver stages. The operating mode for static or clocked activation of the outputs can be determined by the connection pin T _Aus with the non-inverting input of the comparator K₅, and the activation takes place statically when T _{Aus is} connected to the supply voltage U _s . Connection with reference potential leads to clocked activation.

The non-inverting inputs of the comparators K₄ and K₃ are connected to each other and led out to the connection LD.
The output of the comparator K₄ is connected to the output of the comparator K₅.
The input LD senses the voltage of the vehicle electrical system.

If the voltage level of the on-board voltage, which is available via a voltage divider at the connection LD, below a set reference _voltage U _Ref1 , which is present at the inverting input of the comparator K₄, the clocked activation of the relays is prevented via the comparator _output of K₄.

In the event of positive voltage peaks and high interference pulses, the driver transistors of the driver stages are switched to the conductive state via the output of the comparator K₃, at the inverting input of which the reference _voltage U _Ref2 is located. In addition, with positive Overvoltages prevented any short-circuit interrogation.

Master:

PP an Us

Allein:

PP offen

Slave:

PP an Masse

Cascading (master-slave operation) of the receiving device:
The master or slave is determined by connecting the programming pin PP:

Master:

PP to Us

Alone:

PP open

Slave:

PP to ground

In the master operation mode, the oscillator OSZ _E at pin O _E is wired with a RC member and the clock output TA _E is active. If the receiver is operated alone, TA _{E is} blocked.

In the slave mode, the oscillator is locked and must be controlled by the master's clock output, the slave's clock output is locked.

Data recognition: The master recognizes the start bit and decodes the first 8 information bits.
The slave also recognizes the start bit, but decodes the second 8 information bits.

Except for the synchronous clock control, the functions of the master and slave run independently of each other.

FIG. 5 shows a type of connection of the transmission device S _o . In this case, the supply voltage is supplied to the transmitting device via the data transmission link Ü. For this purpose, the resistor R _p in Figure 1 is replaced by the diode D _p , the cathode with the Connection pin U _{S of} the transmitter device S _o and the anode are connected directly to the data transmission path Ü.

The circuit blocks shown in FIGS. 3 and 4 can be integrated completely monolithically.

Claims (12)

1. Circuit arrangement for serial data transmission including a transmitting device (S) having a plurality of parallel bit items of input information (I_En), a serial data transmission path (Ü) and a receiving device (E) by means of which the transmitted data are converted into corresponding parallel bit items of output information (I_An) for the control of adjusting members (St) or logic circuits, wherein, on the data transmission path (Ü), the data to be transmitted form a data word (W) which is made up of a start pulse (SI), a plurality of information units corresponding to the number of the parallel bit items of input information which form a data block (DB) and a defined data pause (DP), characterised in that, the number of the parallel bit items of input and output information (I_En, I_An) is increased by cascading a plurality of transmitting or receiving devices (S_n, E_n) of the same kind whereby, at any one time, under synchronous clock control, one transmitting device and one receiving device (S_o, E_o) serve as master stage and the remaining transmitting and receiving devices as slave stages by means of an inbuilt master-slave programming stage (MS), in such a way that, on the data transmission path (Ü), the data word (W) is modified by the joining together sequentially of a correspondingly increased number of data blocks (DB), respectively having the same number of information units per data block (DB), whereby stores (SPA, SPZ, SPO) for the multiple comparison increase the security of the data transmission.
2. Circuit arrangement in accordance with Claim 1, characterized in that, by the cascading of a plurality of transmitting and receiving devices of the same kind, the generation of the data word (W) on the data transmission path (Ü) has the consequence of a shortening of the data pause or lengthening of the data word or increasing of the transmission frequency, and the joining together sequentially of the data blocks results from a cascading circuit (KD) and an externally programmable memory device (MS) in the transmitting device (S), whereby the sequence of the individual data blocks on the data transmission path (Ü) is established and, at the receiving devices (E) end, the individual data blocks are assigned to the corresponding receiving devices (E_n) by a corresponding programmable memory device (BA).
3. Circuit arrangement in accordance with Claim 1 or 2, characterised in that, the data output of the transmitting device (S) onto the data transmission path (Ü) is effected by a push-pull output stage (GT) having a current limiter.
4. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, by means of a sequence controller (A) in the receiving device (E), a latch (SPA), a downstream buffer store (SPZ) to which an output store (SPO) is connected downstream, a first comparator (K₁), which compares the content of the latch (SPA) with the content of the buffer store (SPZ) and a second comparator (K₂), which compares the content of the buffer store (SPZ) with the content of the output store (SPO) and a counter (Z₂), the security of transmission of transmitting device (S) and data transmission path (Ü) vis a vis disturbances is improved by repeated interrogation of the same items of input information (I_En) and subsequent comparison of the received bit pattern in the comparators (K₁, K₂) with subsequent incrementing of the counter (Z₂) upon equivalence until a defined desired number is reached, or by resetting the counter (Z₂) upon non-equivalence and renewed interrogation of the items of input information (I_En).
5. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, upon short circuit or interruption of the data transmission path (Ü), in the receiving device (E), all the driver stages (Tr) of the parallel bit outputs are blocked after a defined response time.
6. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, the data transmission path (Ü) consists of an electrical connection line or a a glass fibre having an opto-electric transmitting device at the transmitting end and an opto-electric receiving unit at the receiving end.
7. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, an interruption of the data transmission path (Ü) is indicated optically by a light emitting diode (DK) or acoustically by an electro acoustic transducer unit, in that, one of the parallel bit items of input information (I_En) remains constantly set to reference potential and, in the assigned parallel bit driver stage, the light emitting diode or electro acoustic transducer unit is connected-up.
8. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, the feed voltage supply of the transmitting device is effected separately or via the data transmission path (Ü).
9. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, the parallel bit driver stages (Tr) of the receiving device (E) are switched into the conductive state for large damage-causing peak voltages of the supply voltage.
10. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, the parallel bit output information units (I_An) when used for the control of relays as end-users are selectively controlled statically or clock pulsed for minimisation of the power loss.
11. Circuit arrangement in accordance with any of the preceding Claims, characterised in that, the parallel bit driver stages of the receiving device (E) are tested for short circuit condition of the load connected thereto by repeated successive interrogation of the collector emitter voltages during a time frame in which the driver stages (Tr) in the receiving device (E) are switched into the conductive state.
12. Circuit arrangement in accordance with any of the preceding Claims, characterised by the use in the motor vehicle electronics field.

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