EP0229948A2 - Circuit de transmission de données en série - Google Patents

Circuit de transmission de données en série Download PDF

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Publication number
EP0229948A2
EP0229948A2 EP86116724A EP86116724A EP0229948A2 EP 0229948 A2 EP0229948 A2 EP 0229948A2 EP 86116724 A EP86116724 A EP 86116724A EP 86116724 A EP86116724 A EP 86116724A EP 0229948 A2 EP0229948 A2 EP 0229948A2
Authority
EP
European Patent Office
Prior art keywords
data
bit
data transmission
circuit arrangement
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86116724A
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German (de)
English (en)
Other versions
EP0229948A3 (en
EP0229948B1 (fr
Inventor
Hartmut Hantsch
Josef Mahalek
Peter Dr. Thoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bayerische Motoren Werke AG
Conti Temic Microelectronic GmbH
Original Assignee
Bayerische Motoren Werke AG
Telefunken Electronic GmbH
Temic Telefunken Microelectronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bayerische Motoren Werke AG, Telefunken Electronic GmbH, Temic Telefunken Microelectronic GmbH filed Critical Bayerische Motoren Werke AG
Publication of EP0229948A2 publication Critical patent/EP0229948A2/fr
Publication of EP0229948A3 publication Critical patent/EP0229948A3/de
Application granted granted Critical
Publication of EP0229948B1 publication Critical patent/EP0229948B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
    • G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
    • G08C15/12—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division the signals being represented by pulse characteristics in transmission link
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C25/00—Arrangements for preventing or correcting errors; Monitoring arrangements

Definitions

  • the invention relates to an electronic circuit arrangement for serial data transmission with a transmitting device with a plurality of bit-parallel input information, a serial data transmission path and a receiving device, via which the transmitted data are converted into bit-parallel output information for controlling actuators or logic circuits, the data to be transmitted being transmitted on the data transmission path form a data word, which is composed of a start pulse, several information units corresponding to the number of bit-parallel input information that form a data block, and a defined data pause.
  • bit-parallel signals into bit-serial signals or the reversal of this process is a necessity in remote data processing or telex communication.
  • local computer network networks also make use of this conversion if, for example, a terminal is installed in a different wing of the building than the computer.
  • the data to be transmitted are defined by the ASCII code (American Standard Code for Information Interchange) and the levels on the transmission lines are standardized in special standards such as the RS 232 voltage interface (CCITT recommendation V24).
  • a microprocessor solution for serial data transmission is too expensive if, for example, switch positions for different consumers are to be converted into a serial data word as parallel input information in order to control bit-parallel relays as actuators on the receiver side corresponding to the switch positions .
  • bit-parallel input information is expanded via the I / 0 ports with appropriate addressing and software programming.
  • the present invention is therefore based on the object of specifying a circuit arrangement for converting bit-parallel to bit-serial data and vice versa, which requires little circuit complexity and does not require any software, and that the number of bit-parallel input or output information can be changed if necessary.
  • This object is achieved according to the invention in that the number of bit-parallel input and output information can be changed by cascading a plurality of similar transmission or reception devices and thereby the data word on the data transmission path is changed accordingly and by sequentially joining together a corresponding number of data blocks, each with the same number of information units per data block.
  • the block diagram shown in FIG. 1 is composed of a plurality of similar transmission devices S o , S 1 ,... S n , a data transmission path U and a number of reception devices E 0 , E 12 .
  • Each transmission device S n has an equal number of parallel input information I En , in the example shown there are eight, which, according to the arrangement of the n transmission devices S n, are sequentially combined on the data transmission path U to form a data word, as shown in FIG. 2.
  • the input information I En is converted into the same number of corresponding parallel output information I An in the assigned receiving devices E n in order to control relays as final control elements (St) or directly logic circuits.
  • the data word in FIG. 2 consists of a start pulse SI with a pulse duration of, for example, 312 ⁇ s, which is followed by several data blocks DB corresponding to the number of bit-parallel input information, followed by a defined data pause DP.
  • a data block consists of a synchronization bit with, for example, 156 us, a subsequent information bit of the same length of time, followed by two zero bits each of 156 microseconds in duration.
  • the frequency divider stage T consists of a chain of feedback bistable flip-flops, for example D flip-flops, so that different frequency divider ratios are present, and the divided frequency positions are used to form the data word via decoding circuits according to the invention, such as start pulse decoder SID, cascade rest decoder KD, pulse-pause decoder PPD, release decoder FD and scan-pulse decoder SCD linked together, in addition, the frequency divider stage T controls a delay circuit VZ.
  • the pulse scheme shown in Figure 6 shows the output signals of the individual decoding circuits.
  • the same operating voltage supply unit feeds a voltage divider from the two resistors R 2 , R 3 , the connection node of which is fed to the non-inverting input of the comparator stage K 7 .
  • the input information I En shows a logic high level greater than 2.5 V, for example, at the time of the pending scan pulse SCI n , this state is interpreted as an open switch and the output signal of the comparator K 1 is logic zero or low potential. Conversely, if the input information is logic zero or is at a low level, that is to say the switch is closed, the output signal of the comparator K 1 is logic 1 or high level.
  • the output signals from comparator stage K 7 and release decoder FD are linked via an AND gate AND 1 , the output signal of which is fed to an input of a second OR gate OR 2 with several inputs.
  • the output signals of the start pulse decoder SID and the pulse pause decoder PPD are fed to the further inputs of this OR gate.
  • Via an amplifier V l with the data input slave DES connection the data of the downstream transmission device, for example S 1 , which is operated as a slave, is fed to a further input of the OR gate OR 2 , the output of which drives a push-pull output stage GT, the output signal of which Represents data word on the data transmission link Ü.
  • the push-pull output stage GT is blocked for sending a data word W immediately after the supply voltage U s is applied via the output of the delay circuit VZ for a defined period of time, which is determined by counting a specific frequency position of the divider stage T.
  • the output signal of the cascade reset decoder KD is fed to the connection for the cascade reset output KRA via a second amplifier circuit V 2 .
  • the signal of the fundamental frequency f 0 is present at the connection of the clock output TA via a third amplifier V 3 .
  • the supply voltage supply unit U stab / POR is supplied with a supply voltage U s , from which the stabilized voltage U stab is derived.
  • the data word W shown in FIG. 6p begins with a start pulse of, for example, 312 microseconds in duration, followed by eight data blocks DB each with a duration of 624 microseconds, each data block starting with a synchronization bit of 156 microseconds in duration. It is followed by the scanned input information I En , with a logical 0 meaning that the switch in question is closed. In the example in FIG. 6p, every second switch is closed. The information bit is followed by two zero bits of 156 us each.
  • the frequency divider stages T and the pulse-pause decoder PPD can be blocked at their cascade reset input KRE at a logic zero level and released at a high level.
  • the switching of these levels is carried out in cascading operation in master-slave mode by the cascade reset signal, which is generated in the cascade reset decoder KD and is available at the cascade reset output KRA of the master, and the slave-operated downstream transmission device is supplied.
  • a galvanically coupled electrical connecting line can be used as data transmission path 0. But it is also an optoelectronic transmission gungsstrekke possible, which consists for example on the transmitter side of a light-emitting diode LED, which is driven by the push-pull output stage GT with the connection DA of the data output of the transmission device.
  • This light-emitting diode pulses the data word W in an electrically isolated manner, for example via a glass fiber, to a phototransistor, which is arranged on the receiver side and controls the downstream receiving device.
  • the data input DE of the receiving device E is connected to the inverting input of a comparator stage K 6 and to the cathode of a reverse zener diode Z 2 , the anode of which is connected to the reference potential.
  • the non-inverting input of this comparator is connected to a reference voltage via the center tap of a voltage divider consisting of resistors R5, R6.
  • the received data word W is digitally processed to a defined voltage level by the comparator K 6 for further processing in the receiving device E and is supplied to a start pulse detection circuit STE, a scanning pulse generator stage AP and an input of an AND gate AND 2.
  • the AND gate AND 2 is released when the start pulse has been detected in the start pulse detection circuit STE and the other input of the AND gate AND Z is controlled with this signal.
  • the start pulse detection circuit is based on a divided frequency position of a frequency divider stage controlled the receiving device T E , in which after the end of the data pause with the first negative edge it is checked by counting whether a minimum pulse duration is present which can be interpreted as a start pulse.
  • the frequency divider stage T E is used for this purpose by an oscillator circuit OSZ E tung driven to the terminal O E of the Empfangseinrich- whose Grundfreq uenzla g ef oE approximately 4 times as large as that of the transmitting device.
  • the oscillator OSZ E can be blocked or enabled via the output of an operating mode memory BA by setting its connection, the programming pin PP, to high or low potential.
  • the basic frequency f oE of the oscillator OSZ E is additionally fed to a clock output stage TA with the connection TA E , the function of which is also determined by a corresponding control signal from the operating mode memory BA.
  • the frequency divider stage T E controls further modules of the receiving device E with differently divided frequency positions. These include the scanning pulse generator stage AP, a data end decoder DED, which recognizes the end of the transmitted data and communicates this point in time to a sequence control A.
  • the sequence control A is also controlled by different frequency positions of the divider stage T E.
  • the further processing of the received data word takes place via a first counting device Z 1 , which is controlled via a further output signal of the operating mode memory BA and accordingly counts out the first eight bits as master receiver or the second eight bits as slave receiver.
  • the counter Z l is also supplied with the output signal of the AND gate AND 2 .
  • the output of the counter Z 1 and the output of the scanning pulse generator stage AP control a data decoding circuit DD, the control lines of which assume a distribution function by being fed to a clock buffer SPA, which consists of clock-controlled D flip-flops, at the clock inputs thereof .
  • the output signal of the AND gate AND 2 which is identical to the data word, is present at all data inputs of these D flip-flops.
  • the buffer SPA is followed by an identical buffer SPZ.
  • the information read into the buffer memory SPA is compared with the content of the intermediate memory SPZ after the end of data has been recognized.
  • a second counter Z 2 which works as a 4 counter, is counted up one level.
  • the data contents of the buffer memory SPA and the intermediate memory SPZ are compared in the comparator stage K 1 , which emits a control signal to the counter Z 2 and the sequential control system in the event of equivalence.
  • the counter Z 2 is reset via the sequence control A. This also controls the memories SPA, SPZ and SPO and the comparators K 1 and K 2 . After each comparison, the data is transferred from the SPA buffer to the buffer. After four equivalents, the content of the intermediate memory SPZ is compared with the content of the output memory SPO connected downstream via a comparator K 2 . In the event of equivalence, the counter Z 2 is reset since the input information I En has not changed.
  • the information is transferred from the buffer SPZ to the output memory SPO and transferred to the driver stages downstream of the output memory SPO, where it is available as bit-parallel output information I An for controlling actuators or logic circuits stand.
  • An output of the comparator K 2 and a control line of the sequence control are fed to a short-circuit detection circuit KS, by means of which, after approximately 35 ms after the data output of the output memory on the driver stages, these are checked for short-circuit behavior for approximately 10 ms.
  • the collector-emitter voltages of the active driver stages which are designed as open-collector transistors with the connections TRA or I A " , are queried four times in succession via a comparator stage to ensure that there is no interference pulse. If there is a short-circuit signal for approx. 10 ms on, the corresponding transistor is blocked. The blocked state remains stored and can only be deleted by switching off and switching on the supply voltage supply unit U stab / POR again by a so-called "Power On Reset", in the same way as that of the transmitting device is executed.
  • a further protective measure for the driver stages is carried out by a safety test device PR, which is controlled by a frequency position of the frequency divider stage T E. This ensures that all driver outputs are blocked after a defined time of approx. 50 ms in the event of a break or short circuit in the data transmission path Ü.
  • the fault can be indicated optically or acoustically when input information from the transmitter device is fixed at a logic low level with reference potential and the corresponding output is wired according to FIG.
  • Further modules of the receiver circuit are three comparators K 3 , K 41 K 5 , the output signals of which act on the driver stages.
  • relays are controlled by the output stages, they can be statically controlled for approx. 120 ms after switching on. The short-circuit test of the outputs also takes place during this time. The outputs can then be driven in a clocked manner, with the fundamental frequency of the oscillator of the receiver circuit f oE , in order to reduce the power loss in the driver stages.
  • the operating mode for static or clocked activation of the outputs can be defined by the connection pin T Aus with the non-inverting input of the comparator K 5 , and the activation takes place statically when T Aus is connected to the supply voltage U. Connection with reference potential leads to clocked activation.
  • the non-inverting inputs of the comparators K 4 and K 3 are connected to one another and led out to the connection LD.
  • the output of the comparator K 4 is connected to the output of the comparator K 5 .
  • the input LD senses the voltage of the vehicle electrical system.
  • the driver transistors of the driver stages are switched to the conductive state via the output of the comparator K 3 , at the inverting input of which the reference voltage U Ref2 is located.
  • the comparator K 3 the comparator K 3
  • the comparator K 3 the comparator K 3
  • the oscillator In the slave mode, the oscillator is locked and must be controlled by the master's clock output, the slave's clock output is locked.
  • the master recognizes the start bit and decodes the first 8 information bits.
  • the slave also recognizes the start bit, but decodes the second 8 information bits.
  • FIG. 5 shows a type of connection of the transmission device S 0 .
  • the supply voltage is supplied to the transmitting device via the data transmission link Ü.
  • the resistor R p in Figure 1 is replaced by the diode D p , the cathode with the Connection pin U s of the transmitter device S o and the anode are connected directly to the data transmission path Ü.
  • circuit blocks shown in FIGS. 3 and 4 can be integrated completely monolithically.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Error Detection And Correction (AREA)
  • Communication Control (AREA)
EP19860116724 1985-12-20 1986-12-02 Circuit de transmission de données en série Expired - Lifetime EP0229948B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19853545293 DE3545293A1 (de) 1985-12-20 1985-12-20 Schaltungsanordnung zur seriellen datenuebertragung
DE3545293 1985-12-20

Publications (3)

Publication Number Publication Date
EP0229948A2 true EP0229948A2 (fr) 1987-07-29
EP0229948A3 EP0229948A3 (en) 1989-04-26
EP0229948B1 EP0229948B1 (fr) 1993-03-17

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EP19860116724 Expired - Lifetime EP0229948B1 (fr) 1985-12-20 1986-12-02 Circuit de transmission de données en série

Country Status (4)

Country Link
US (1) US5067076A (fr)
EP (1) EP0229948B1 (fr)
JP (1) JPH0771087B2 (fr)
DE (2) DE3545293A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2647998A1 (fr) * 1989-06-02 1990-12-07 Kuroda Precision Ind Ltd Systeme de transmission de signaux de commande/surveillance

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JP2637992B2 (ja) * 1987-09-14 1997-08-06 黒田精工株式会社 直並列変換形遠隔制御方式
JP2723232B2 (ja) * 1987-09-30 1998-03-09 黒田精工株式会社 並列のセンサ信号の直列伝送方式
US5461561A (en) * 1991-09-10 1995-10-24 Electronic Retailing Systems International Inc. System for recognizing display devices
US5598442A (en) * 1994-06-17 1997-01-28 International Business Machines Corporation Self-timed parallel inter-system data communication channel
US5724554A (en) * 1994-11-30 1998-03-03 Intel Corporation Apparatus for dual serial and parallel port connections for computer peripherals using a single connector
ES2177443B1 (es) * 2000-12-26 2005-03-01 Lear Automotive (Eeds) Spain, S.L. Sistema distribuido y procedimiento de adquisicion de datos a distancia, en paquetes con protocolo de comunicacion que optimiza la velocidad de transmision.
DE10102995B4 (de) * 2001-01-24 2006-05-24 Robert Bosch Gmbh Datenbus für Rückhaltemittel in einem Fahrzeug
DE10105857A1 (de) * 2001-02-08 2002-08-14 Marten Saal Kaskadierbarer Ein-/Ausgabedecoder
CN117435426B (zh) * 2023-10-18 2024-05-07 成都观岩科技有限公司 一种芯片内串行数据溢出校验方法

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US4227075A (en) * 1977-08-30 1980-10-07 International Telephone And Telegraph Corporation Multichannel fiber optic control system
CA1170723A (fr) * 1980-05-26 1984-07-10 United-Carr Division Of Trw Canada Ltd. Systeme de telecommande a couplage optique
EP0153434A1 (fr) * 1983-02-23 1985-09-04 Petri AG Installation de commande électrique pour véhicules

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US4227075A (en) * 1977-08-30 1980-10-07 International Telephone And Telegraph Corporation Multichannel fiber optic control system
CA1170723A (fr) * 1980-05-26 1984-07-10 United-Carr Division Of Trw Canada Ltd. Systeme de telecommande a couplage optique
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2647998A1 (fr) * 1989-06-02 1990-12-07 Kuroda Precision Ind Ltd Systeme de transmission de signaux de commande/surveillance

Also Published As

Publication number Publication date
JPH0771087B2 (ja) 1995-07-31
EP0229948A3 (en) 1989-04-26
DE3545293C2 (fr) 1989-01-05
JPS62159548A (ja) 1987-07-15
US5067076A (en) 1991-11-19
DE3688060D1 (de) 1993-04-22
DE3545293A1 (de) 1987-07-02
EP0229948B1 (fr) 1993-03-17

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