EP0096096A1 - Procédé pour régler l'angle d'inclination dans du polysilicum - Google Patents

Procédé pour régler l'angle d'inclination dans du polysilicum Download PDF

Info

Publication number
EP0096096A1
EP0096096A1 EP82105173A EP82105173A EP0096096A1 EP 0096096 A1 EP0096096 A1 EP 0096096A1 EP 82105173 A EP82105173 A EP 82105173A EP 82105173 A EP82105173 A EP 82105173A EP 0096096 A1 EP0096096 A1 EP 0096096A1
Authority
EP
European Patent Office
Prior art keywords
polysilicon
layer
hydrogen peroxide
ammonia
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82105173A
Other languages
German (de)
English (en)
Other versions
EP0096096B1 (fr
Inventor
Wolfgang Augstein
Peter Frasch
Blanka Ivancic
Markus Dr. Dipl.-Chem. Zügel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
International Business Machines Corp
Original Assignee
IBM Deutschland GmbH
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH, International Business Machines Corp filed Critical IBM Deutschland GmbH
Priority to DE8282105173T priority Critical patent/DE3277343D1/de
Priority to EP82105173A priority patent/EP0096096B1/fr
Priority to JP58067174A priority patent/JPS58220431A/ja
Priority to US06/494,755 priority patent/US4452881A/en
Publication of EP0096096A1 publication Critical patent/EP0096096A1/fr
Application granted granted Critical
Publication of EP0096096B1 publication Critical patent/EP0096096B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist

Definitions

  • the invention relates to a method for adjusting the edge angle of openings in a polysilicon layer, in which a resist mask is produced on the polysilicon layer to be etched in a photolithographic method and the exposed polysilicon is subsequently etched.
  • the method according to the invention is used in the production of integrated memory arrangements with a plurality of memory cells arranged in a semiconductor substrate, each of which has a field effect transistor (FET) and a capacitor connected in series with it.
  • FET field effect transistor
  • the physical structures of this field effect transistor memory arrangement and a suitable process for producing these structures are described in German Patent 23 63 466.
  • a characteristic of this process, which will be discussed in more detail in the specific description, is the multilayer gate insulation (oxide nitride) Shielding layer made of p-doped polycrystalline silicon and a diffusion source made of doped oxide.
  • the application of the method according to the invention is not limited to the manufacture of the structures mentioned above, but can also be used in future semiconductor technologies.
  • edge angles of openings in the shielding layer made of polysilicon must be set to values below 45 °.
  • edge angles cannot be produced in p-doped polysilicon layers using graphic methods; typically steeper angles of the order of 60 ° to 70 ° are obtained.
  • the object of the invention is therefore to provide a method for adjusting the edge angle of openings in a polysilicon layer, in which the photoresist adhesion in the photolithographic process carried out is influenced by a suitable pretreatment in such a way that during the subsequent etching of the exposed areas of the polysilicon layer, flat edge angles be preserved.
  • the object of the invention is achieved according to claim 1 in that the polysilicon layer is treated with a mixture of 5 parts of water and 1 to 3 parts of ammonia and 0.25 to 1 part of hydrogen peroxide before applying the photoresist layer.
  • the edge angle can also be influenced by the selection of a suitable temperature during the treatment.
  • the so-called side path effect which relates to the formation of a parasitic current path between the source and drain of an FET when the gate is positively acted upon and is caused by movably charged contaminants near the edge of the metal gate, can be effectively prevented.
  • FIG. 3 shows a scanning electron microscope image of the etched edge of an opening in the polysilicon layer.
  • a substrate (1) made of p-doped silicon is shown, on the back of which there is an amorphous silicon layer (2) which serves to control leakage currents and was produced by implantation of argon with a dose and energy sufficient for amorphization .
  • silicon dioxide (3) doped with arsenic is deposited on the wafer (1) in a reactor and undoped oxide from this is deposited from the vapor phase.
  • the doped oxide layer deposited over the entire surface is structured in a photolithographic process using a first mask.
  • As 2 0 3 diffuses from the oxide zones (3) to the silicon substrate (1) and is reduced there:
  • This reaction is carried out in an oxidizing atmosphere, which prevents the formation of an arsenic layer.
  • a driving-in step in pure nitrogen follows which the arsenic is driven to the desired depth.
  • a thin thermal oxide layer grows on the wafer surface, which serves as a shield for the boron implantation (6) that now follows.
  • the implantation of boron which leads to a doping profile of approximately 1.8 x 1016 At / cm 3 on the wafer surface, serves to set a constant threshold voltage.
  • the doped oxide (3) above the storage node (5) is removed in a photolithographic process using a second mask, while it is retained over the bit line (4). After removing the photoresist, the thin driving oxide is also removed from the wafer surface. In this state, the memory cell is shown in Fig. La.
  • insulators and conductors that are used to control the surface condition of the wafer are manufactured.
  • an oxide layer (7) is thermally grown on the wafer (1). This is used as gate insulation of the field effect transistor.
  • a silicon nitride layer (8) is then deposited from the vapor phase. The thickness ratio of both layers is matched to the desired properties of the integrated circuits to be produced.
  • a polycrystalline silicon layer (9) is deposited over the oxide / nitride insulation and is doped with an acceptor material, for example with boron, for high conductivity.
  • the method according to the invention is incorporated into the process sequence.
  • the polysilicon (9) is then removed in the areas which are provided as a gate (10) and as contact points to the silicon (not shown) in a photolithographic process using a third mask. This state is shown in Fig. 1b.
  • a second oxide layer (11) is formed on the polycrystalline silicon layer (9) by thermal oxidation in such a way that the edges of the layer 9 are also completely covered with oxide.
  • the polysilicon (9) is converted into oxide in a layer thickness of approximately 300 nm. Since silicon dioxide grows very slowly on silicon nitride, only a very thin oxide layer (IIa) is formed at the same time on the nitride layer (8) exposed in the gate opening (10).
  • An aluminum layer (12) is then evaporated onto the surface of the device.
  • a fifth mask is structured using a fifth mask. The structuring takes place according to a metal lifting process, which is described in German Patent 26 17 914. The state after completion of the first metallization is shown in Fig. 1c. Insulated parts of the aluminum layer (12) establish the electrical connection between the polysilicon shielding layer (9) and the semiconductor substrate (1).
  • the surface of the structure is covered by a sprayed-on quartz layer, which is used for protection and passivation.
  • the application of a further metallization will not be discussed in more detail in the context of this description.
  • a suitable pretreatment of the polysilicon is to ensure that in the subsequent photolithographic process the adhesion of the resist to the polysilicon layer (9) in the vicinity of the gate (10) to be etched and the contact points to be etched is modified such that the etching following the exposure, development and curing of the photoresist can be obtained through the photoresist mask in the polysilicon layer etching angle between 15 ° and 35 °.
  • steeper etching angles are obtained due to the doping profile of the polysilicon and if one works according to conventional photolithographic processes.
  • pretreatment solutions containing ammonia, hydrogen peroxide and water which are used in semiconductor technology to remove organic contaminants from wafer surfaces, are particularly suitable for influencing the photoresist adhesion if the individual constituents in the solution in a certain concentration ratio are included.
  • the steepness of the edge angle can be further influenced by the selection of a specific temperature range. Experimental results have shown that the etching angles become steeper with increasing ammonia content and that they become flatter with increasing hydrogen peroxide content in the solution. Solutions containing 5 parts water, 1 to 3 parts ammonia and 0.25 to 1 part hydrogen peroxide are particularly suitable. Concentrated aqueous solutions of ammonia (28 to 29%) and hydrogen peroxide (30%) are used to prepare the solutions.
  • the pretreatment solutions can be used as long as active hydrogen peroxide is still in the concentration range described above is available. For practical reasons, a standing time of 4 hours has proven itself.
  • Substrates (1) which are provided with a polysilicon layer (9) are treated with an aqueous ammoniacal hydrogen peroxide solution.
  • the treatment solution contains 5 parts water, 1 to 3 parts ammonia and 0.25 to 1 part hydrogen peroxide.
  • the bath temperature is advantageously between 40 and 70 ° C. The pretreatment is carried out within two hours.
  • the wafers pretreated in this way are then coated with an adhesion promoter, for example with hexamethyldisilazane.
  • an adhesion promoter for example with hexamethyldisilazane.
  • a positive photoresist dissolved in a mixture of organic solvents is applied.
  • a resist available from Shipley under the trade name AZ 1350J which consists of an m-cresol-formaldehyde novolak resin, is suitable as such and a diazoketone sensitizer, which is identified as 4'-2'-3'-dihydroxybenzophenone ester of 1-0xo-2-diazonaphthalin-5-sulfonic acid.
  • the photoresist layer is then dried for 3 to 15 minutes at 80 to 100 ° C. and exposed in a known manner.
  • the exposure time depends on the size of the motif of the desired structures and depends on the exposure device used.
  • the exposed photoresist layer is developed in a known manner in a developer based on sodium dihydrogen phosphate, sodium metasilicate and sodium hydroxide and cured at 130 ° C. for about 15 minutes.
  • the polysilicon layer (9) is etched in a NNO 3 -HF-H 2 O mixture.
  • the measurement of the edge angle of the openings in the polysilicon layer is performed with the scanning electron microscope (SEM) at a 90 inclination 0 of the sample.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)
EP82105173A 1982-06-14 1982-06-14 Procédé pour régler l'angle d'inclination dans du polysilicum Expired EP0096096B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE8282105173T DE3277343D1 (en) 1982-06-14 1982-06-14 Method of adjusting the edge angle in polysilicon
EP82105173A EP0096096B1 (fr) 1982-06-14 1982-06-14 Procédé pour régler l'angle d'inclination dans du polysilicum
JP58067174A JPS58220431A (ja) 1982-06-14 1983-04-18 多結晶シリコン層中の開孔の端部角度を設定する方法
US06/494,755 US4452881A (en) 1982-06-14 1983-05-16 Method of adjusting the edge angle in polysilicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP82105173A EP0096096B1 (fr) 1982-06-14 1982-06-14 Procédé pour régler l'angle d'inclination dans du polysilicum

Publications (2)

Publication Number Publication Date
EP0096096A1 true EP0096096A1 (fr) 1983-12-21
EP0096096B1 EP0096096B1 (fr) 1987-09-16

Family

ID=8189085

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82105173A Expired EP0096096B1 (fr) 1982-06-14 1982-06-14 Procédé pour régler l'angle d'inclination dans du polysilicum

Country Status (4)

Country Link
US (1) US4452881A (fr)
EP (1) EP0096096B1 (fr)
JP (1) JPS58220431A (fr)
DE (1) DE3277343D1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469370A2 (fr) * 1990-07-31 1992-02-05 Gold Star Co. Ltd Procédé d'attaque pour obtenir des parois inclinées

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970002427B1 (en) * 1994-01-14 1997-03-05 Lg Semicon Co Ltd Fine patterning method of photoresist film
US7022592B2 (en) * 2003-10-03 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Ammonia-treated polysilicon semiconductor device
TWI258201B (en) * 2005-02-16 2006-07-11 Powerchip Semiconductor Corp Method for manufacturing semiconductor device and plug
CN104409324A (zh) * 2014-11-12 2015-03-11 吉林华微电子股份有限公司 能够避免沾污的多晶硅磷掺杂后处理清洗方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0001550A1 (fr) * 1977-10-25 1979-05-02 International Business Machines Corporation Dispositif semiconducteur à intégration avec de petites structures et procédé pour sa fabrication
DE2363466C3 (de) * 1973-01-02 1980-10-02 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung
DE2617914C2 (de) * 1975-05-09 1982-05-27 International Business Machines Corp., 10504 Armonk, N.Y. Verfahren zum Herstellen von Mustern eines dünnen Films auf einem Substrat bei der Herstellung von integrierten Schaltungen

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3827908A (en) * 1972-12-11 1974-08-06 Ibm Method for improving photoresist adherence
US3811076A (en) * 1973-01-02 1974-05-14 Ibm Field effect transistor integrated circuit and memory
US3841926A (en) * 1973-01-02 1974-10-15 Ibm Integrated circuit fabrication process
JPS5218098B2 (fr) * 1973-05-04 1977-05-19

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2363466C3 (de) * 1973-01-02 1980-10-02 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung
DE2617914C2 (de) * 1975-05-09 1982-05-27 International Business Machines Corp., 10504 Armonk, N.Y. Verfahren zum Herstellen von Mustern eines dünnen Films auf einem Substrat bei der Herstellung von integrierten Schaltungen
EP0001550A1 (fr) * 1977-10-25 1979-05-02 International Business Machines Corporation Dispositif semiconducteur à intégration avec de petites structures et procédé pour sa fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0469370A2 (fr) * 1990-07-31 1992-02-05 Gold Star Co. Ltd Procédé d'attaque pour obtenir des parois inclinées
EP0469370A3 (en) * 1990-07-31 1992-09-09 Gold Star Co. Ltd Etching process for sloped side walls

Also Published As

Publication number Publication date
DE3277343D1 (en) 1987-10-22
JPH0139647B2 (fr) 1989-08-22
US4452881A (en) 1984-06-05
EP0096096B1 (fr) 1987-09-16
JPS58220431A (ja) 1983-12-22

Similar Documents

Publication Publication Date Title
DE2703957C2 (de) FET-Ein-Element-Speicherzelle und Verfahren zu ihrerHerstellung
EP0010624B1 (fr) Procédé pour la réalisation d'ouvertures de masque très petites pour la fabrication de circuits intégrés à semiconducteurs
DE3939319C2 (de) Verfahren zum Herstellen eines asymmetrischen Feldeffekttransistors
DE1764056C2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE4224793C2 (de) Dünnfilmfeldeffektelement und Herstellungsverfahren dafür
DE3012363C2 (de) Verfahren zur Bildung der Kanalbereiche und der Wannen von Halbleiterbauelementen
DE3019850C2 (fr)
DE2716691A1 (de) Feldeffekttransistor und verfahren zu dessen herstellung
DE2928923C2 (fr)
DE3334333A1 (de) Verfahren zur herstellung eines mos-einrichtung mit selbstjustierten kontakten
EP0000327A1 (fr) Procédé de fabrication de dispositifs semiconducteurs intégrés auto-alignés
DE2916098A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
EP0030640A2 (fr) Procédé pour la formation d'une électrode de porte auto-alignée pour un transistor à effet de champ V-MOS
DE2738384A1 (de) Verfahren zur herstellung eines halbleiters
DE3540422C2 (de) Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen
EP0066730B1 (fr) Structure isolante à couches pour électrode de porte, procédé pour la réalisation et application de cette structure
DE2723374A1 (de) Halbleiterstruktur mit mindestens einem fet und verfahren zu ihrer herstellung
DE2422120B2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
EP0183138A1 (fr) Procédé pour fabriquer des circuits du type transistors MOS à haute densité
DE2621165A1 (de) Verfahren zum herstellen eines metallkontaktes
DE2556038A1 (de) Verfahren zur herstellung von feldeffekttransistoren fuer sehr hohe frequenzen nach der technik integrierter schaltungen
DE2628406A1 (de) Verfahren zum herstellen einer halbleitervorrichtung
EP0096096B1 (fr) Procédé pour régler l'angle d'inclination dans du polysilicum
DE2839933A1 (de) Integrierte schaltung mit isolierendem substrat
DE2111633A1 (de) Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19840426

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 3277343

Country of ref document: DE

Date of ref document: 19871022

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
ET Fr: translation filed
R20 Corrections of a patent specification

Effective date: 19871021

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19920507

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19920601

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19920619

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19930614

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19930614

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19940228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19940301

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST