DK178660B1 - Fremgangsmåde til udnyttelse af dobbelte komparatorer for at lette en præcisionssignalrektificering og timing-system uden signalfeedback - Google Patents
Fremgangsmåde til udnyttelse af dobbelte komparatorer for at lette en præcisionssignalrektificering og timing-system uden signalfeedback Download PDFInfo
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- DK178660B1 DK178660B1 DKPA201270357A DKPA201270357A DK178660B1 DK 178660 B1 DK178660 B1 DK 178660B1 DK PA201270357 A DKPA201270357 A DK PA201270357A DK PA201270357 A DKPA201270357 A DK PA201270357A DK 178660 B1 DK178660 B1 DK 178660B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
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Description
A METHOD OF UTILIZING DUAL COMPARATORS TO FACILITATE A PRECISION SIGNAL RECTIFICATION AND TIMING SYSTEM WITHOUT SIGNAL FEEDBACK
BACKGROUND OF THE INVENTION FIELD OF THE INVENTION
[0001] The present invention relates to comparator circuits and, more particularly, to a method and an associated circuit and of using two comparators to separately compare an input signal of variable amplitude with an upper threshold value and a lower threshold value.
DISCUSSION OF PRIOR ART
[0002] In many electronic circuits, it is desirable to convert an analog sensor output from an analog signal to a digital signal prior to a desired signal processing operation. One prior art solution to convert an analog signal to a digital signal is by using a comparator to logically compare an electrical property of an analog signal input with another input signal such as a nominal desired threshold. This electrical property can be voltage, amperage, or the like. When the electrical property value of the analog signal input crosses the threshold, the output of the comparator transitions.
[0003] At times, background noise is superimposed on the analog signal input. This superposition can create various undesirable amplitude changes on the analog signal input. The background noise can add peaks and valleys to the amplitude of the analog signal input. As these amplitude variations pass through a comparator, the variations can frequently pass back and forth through the threshold level. This frequent amplitude transition across the threshold will also create a frequent transition in the comparator output signal and is often called bounce. This bounce characteristic is often undesirable, and a feedback circuit is sometimes used to control the bounce.
[0004] In order to eliminate some degree of bounce, a comparator may use hysteresis to limit the number of times the analog signal input effectively crosses the threshold. A nominal threshold is selected, in addition to an upper threshold and a lower threshold. The nominal threshold represents the amplitude where the desired output from the comparator is to change. The upper threshold is higher than the nominal threshold, and the comparator signal does not change until the analog signal input crosses the upper threshold. Similarly, the comparator output will not change again until the analog signal input drops below the lower threshold, which is below the nominal threshold. As a result, the hysteresis of the comparator is used to eliminate the spurious switches in comparator output created by the superimposed noise level on the analog signal input. The upper threshold and lower threshold are selected to minimize the bounce while maintaining an accurate comparator output relative to where the analog input signal crosses the nominal threshold. Reference US 3,683,284 in this regard illustrates two level comparators in form of Schmitt trigger circuits, which produces an output signal when an iput signal exceeds a pre-determiend threshold value. A logic circuit generates an output pulse based on the output of the comparators.
[0005] The typical feedback circuit uses this application of hysteresis and a single comparator to evaluate when the analog signal input crosses the upper threshold level and the lower threshold level. After the analog signal input crosses the upper threshold, the feedback circuit will switch the comparator to use the lower threshold. However, in some situations, the analog signal input can initially cross the upper threshold and then cross below the upper threshold before the hysteresis is able to switch to the lower threshold. This situation creates spurious comparator output in the form of rapid fluctuation, or bounce. The bounce will foul the signal processing that occurs in subsequent circuit components. Additionally, this typical solution using a feedback circuit may have propagation delay which will generate an undesired phase shift in the resultant output waveform.
[0006] As such, there is a need for improvements in methods and circuits.
BRIEF DESCRIPTION OF THE INVENTION
[0007] The following presents a simplified summary of the invention in order to provide a basic understanding of some example aspects of the invention. This summary is not an extensive overview of the invention. Moreover, this summary is not intended to identify critical elements of the invention nor delineate the scope of the invention. The sole purpose of the summary is to present some concepts of the invention in simplified form as a prelude to the more detailed description that is presented later.
[0008] The present invention provides a method of electronic signal rectification in accordance with the subject matter of claim 1. The method includes generating a variable amplitude input signal, determining an upper threshold level, and determining a lower threshold level. The method includes inputting the variable amplitude input signal and the upper threshold level into a first comparator. The method includes inputting the variable amplitude input signal and the lower threshold level into a second comparator. The method includes generating a first digital output signal in the first comparator using a hysteresis circuit and a second digital output signal in the second comparator using a hysteresis circuit. The method includes inputting the first digital output signal and the second digital output signal into a logic array. The method includes generating a digital level pulse output signal in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.
[0009] The present invention also provides signal rectification and timing circuit in accordance with claim 5 for receiving a variable amplitude input signal and generating a digital level pulse output signal that transitions at the time the variable amplitude input signal passes through a threshold level. The rectification and timing circuit includes a first comparator for comparing the variable amplitude input signal and a determined upper threshold signal and producing a first digital output signal indicative of the comparison. The circuit includes a hysteresis circuit coupled to the first comparator. The circuit includes a second comparator for comparing the variable amplitude input signal and a determined lower threshold signal and producing a second digital output signal indicative of the comparison. The circuit includes a hysteresis circuit coupled to the second comparator The circuit includes a logic array for receiving the first digital output signal and the second digital output signal and generating the digital level pulse output signal that transitions at the time the variable amplitude input signal passes through a threshold level.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The foregoing and other aspects of the invention will become apparent to those skilled in the art to which the invention relates upon reading the following description with reference to the accompanying drawings, in which: [0011] FIG. 1 is a block diagram illustrating an example of a signal rectification and timing circuit in accordance with an aspect of the invention; [0012] FIG. 2 is a graph illustrating the operation of a signal rectification and timing circuit of FIG. 1 including a variable amplitude input signal, the resultant output signals from two comparators, and the digital level pulse output signal; and [0013] FIG. 3 is a top level flow diagram illustrating a method of operating a signal rectification and timing circuit in accordance with an aspect of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0014] Example embodiments that incorporate one or more aspects of the present invention are described and illustrated in the drawings. These illustrated examples are not intended to be a limitation on the present invention. For example, one or more aspects of the present invention can be utilized in other embodiments and even other types of devices. Moreover, certain terminology is used herein for convenience only and is not to be taken as a limitation on the present invention. Still further, in the drawings, the same reference numerals are employed for designating the same elements.
[0015] An example signal rectification and timing circuit is generally designated 10 within FIG. 1. It is to be appreciated that FIG. 1 merely shows one example and that other examples are contemplated within the present invention. The signal rectification and timing circuit 10 has a variable amplitude input signal 12. The variable amplitude input signal 12 can be the output of a common analog sensor (not shown). Analog sensors produce a change in an electrical property to indicate a change in its environment. The analog sensor output is a signal including changes in an electrical property corresponding to the changes in the sensor’s environment. The electrical property can be a voltage, amperage, or the like. At times, it is desirable to convert the analog sensor output from an analog signal to a digital signal prior to a desired signal processing operation.
[0016] An upper threshold signal 14 and a lower threshold signal 16 are also inputs into the circuit. The upper threshold signal 14 passes through resistor 17 and the lower threshold signal 16 passes through resistor 18 prior to any signal processing. Resistors 17, 18 control the alternating current (AC) and direct current (DC) hysteresis around the comparators which are described below.
[0017] The signal rectification and timing circuit 10 is generally divided into two portions, the upper level threshold comparator side 20 and the lower level threshold comparator side 40. The upper level threshold comparator side 20 includes a first comparator 22. The first comparator 22 is chosen on the basis of being tolerant to the applied voltages in the signal rectification and timing circuit 10 and having adequate speed to condition the first digital output signal 23. The first comparator 22 includes inputs for the variable amplitude input signal 12 and the upper threshold signal 14. The first comparator 22 produces a first digital output signal 23 which represents the polarity of the difference between the amplitude of the upper threshold signal 14 and the variable amplitude input signal 12. The first digital output signal 23 is then used in a hysteresis circuit to limit the bounce of the first comparator 22.
[0018] The upper level threshold comparator side 20 also includes capacitor 24 and capacitor 26. Capacitors 24, 26 are chosen based upon the recommendations of the first comparator 22 manufacturer regarding effective construction of a hysteresis circuit and may not be necessary for all comparators. The upper level threshold comparator side 20 also includes capacitor 28 and resistor 30 which control the AC hysteresis around the first comparator 22 input. The upper level threshold comparator side 20 further includes resistor 32 which controls the DC hysteresis around the first comparator 22. Resistor 34 is chosen based upon the recommendation of the first comparator 22 manufacturer regarding effective construction of a hysteresis circuit and may not be necessary for all comparators. The upper level threshold comparator side 20 further includes resistor 36 which controls the speed of the rising edge of the first digital output signal 23.
[0019] The lower level threshold comparator side 40 includes a second comparator 42. The second comparator 42 is chosen on the basis of being tolerant to the applied voltages in the signal rectification and timing circuit 10 and having adequate speed to condition the second digital output signal 43. The second comparator 42 includes inputs for the variable amplitude input signal 12 and the lower threshold signal 16. The second comparator 42 produces a second digital output signal 43 which represents the polarity of the difference between the amplitude of the lower threshold signal 16 and the variable amplitude input signal 12. The second digital output signal 43 is then used in a hysteresis circuit to limit the bounce of the second comparator 42.
[0020] The lower level threshold comparator side 40 also includes capacitor 44 and capacitor 46. Capacitors 44, 46 are chosen based upon the recommendations of the second comparator 42 manufacturer regarding effective construction of a hysteresis circuit and may not be necessary for all comparators. The lower level threshold comparator side 40 also includes capacitor 48 and resistor 50 which control the AC hysteresis around the second comparator 42 input. The lower level threshold comparator side 40 further includes resistor 52 which controls the DC hysteresis around the second comparator 42. Resistor 54 is chosen based upon the recommendation of the second comparator 42 manufacturer regarding effective construction of a hysteresis circuit and may not be necessary for all comparators. The lower level threshold comparator side 40 further includes resistor 56 which controls the speed of the rising edge of the second digital output signal 43.
[0021] After the hysteresis process at the first comparator 22, the first digital output signal 23 becomes a first logic input signal 60. Similarly, after the hysteresis process at the second comparator 42, the second digital output signal 43 becomes a second logic input signal 62. The first logic input signal 60 and the second logic input signal 62 are inputs into a logic array 64. The logic array 64 combines the first logic input signal 60 and the second logic input signal 62 to form a digital level pulse output signal 70 which has a digital transition where the variable amplitude input signal 12 crossed a threshold. The transition may be precisely at the threshold cross. Within the shown example, the crossed threshold is the upper threshold level. It is to be appreciated that the threshold crossing may be one of the upper or lower threshold levels.
[0022] Some example component values for the circuitry of FIG. 1 include:
Capacitor 24, 26, 44, 46 = per the respective comparator’s manufacturer recommendation, possibly not necessary for all comparators.
Capacitor 28, 48 = 1 pF to 1000 pF Resistor 17, 18 = 0 to 100 kOhm Resistor 34, 54 = per the respective comparator’s manufacturer recommendation, possibly not necessary for all comparators.
Resistor 30, 50 = 1 kOhm to 1 MOhm Resistor 32, 52 = lOkOhm to lOMOhm Resistor 36, 56 = IkOhm to lOOkOhm [0023] The signal rectification and timing circuit 10 eliminates the need for a feedback circuit that is typically used with a single comparator to compare a signal level to both an upper threshold signal 14 and a lower threshold signal 16. The present signal rectification and timing circuit 10 includes a first comparator 22 and a second comparator 42 which individually compare the variable amplitude input signal 12 to an upper threshold signal 14 and a lower threshold signal 16. The elimination of the feedback circuit decreases the propagation delay in the first digital output signal 23 and the second digital output signal 43. The decrease in the propagation delay enables the signal rectification and timing circuit 10 to reduce the phase error in the signal processing at the logic array 64.
[0024] Additionally, the elimination of a feedback circuit in the signal rectification and timing circuit 10 also eliminates the race condition when using the single comparator. The race condition is that in which an input signal crosses a desired threshold more than once before the feedback circuit is able to apply a new threshold value with hysteresis being applied to the comparator. As a result, the output signal of a comparator can have multiple undesired, rapidly occurring signal transitions. The signal rectification and timing circuit 10 eliminates the spurious conditioned signal transitions by using a single comparator for the upper threshold signal 14 and a single comparator for the lower threshold signal 16.
[0025] Other methods to create a digital level pulse output signal 70 having a digital transition precisely where a variable amplitude input signal 12 passed through a threshold level have been attempted. One method is to convert the variable amplitude input signal 12 to a digital signal at the initial portion of a circuit and then use digital signal processing to generate the transition points. This method is limited by current technology that does not support enough analog to digital conversion bandwidth with the necessary bit depth. Furthermore, this method is expensive and cumbersome to accomplish with tools such as firmware.
[0026] Turning to FIG. 2, a graph representing example input signals and output of the signal rectification and timing circuit 10 is shown. The upper portion of the graph includes variable amplitude input signal 12 as it proceeds from left to right over time. As time proceeds, the variable amplitude input signal 12 crosses both the lower threshold signal 16 and the upper threshold signal 14. The nominal threshold 80 is also included in the upper portion of the graph. The lower portion of the graph includes the first logic input signal 60, the second logic input signal 62, and the digital level pulse output signal 70.
[0027] As the variable amplitude input signal 12 crosses the amplitude of the lower threshold signal 16, the second logic input signal 62 switches. This switch represents the result of the second comparator 42 operation. The switch occurs at the same time that the variable amplitude input signal 12 passed through the lower threshold signal 16. The variable amplitude input signal 12 then crosses the upper threshold signal 14 and this causes a switch in the first logic input signal 60. This switch also occurs at the same time that the variable amplitude input signal 12 passed through the upper threshold signal 14.
[0028] Similarly, the variable amplitude input signal 12 then crosses the upper threshold signal 14, causing a switch in the first logic input signal 60. The variable amplitude input signal 12 then crosses the lower threshold signal 16, causing a switch in the second logic input signal 62. The digital level pulse output signal 70 is generated by the logic array 64 as a combination of the first logic input signal 60 and the second logic input signal 62. Each of the switches in the digital level pulse output signal 70 occurs at the time that the variable amplitude input signal 12 crosses a threshold and there is minimal phase shift between the digital level pulse output signal and the variable amplitude input signal.
[0029] Turning to FIG. 3, a method of operating a comparator circuit is described. The method includes the step 102 of generating a variable amplitude input signal 12. The variable amplitude input signal 12 can be derived from any number of standard sensors including, but not limited to sensors detecting: electrical; magnetic; temperature; humidity; force; weight; torque; pressure; motion; vibration; flow; fluid level; fluid volume; light and infrared; or chemistry parameters. The variable amplitude signal input can also be a voltage output from any source.
[0030] The method also includes the step 104 of determining an upper threshold signal 14. The upper threshold signal 14 can be a voltage input from any source, and can be controlled by the operator of the signal rectification and timing circuit 10. The upper threshold signal 14 can be selected to optimize the range between the nominal threshold 80 and the upper threshold signal 14 while minimizing the bounce of the first digital output signal 23.
[0031] The method further includes the step 106 of determining a lower threshold signal 16. The lower threshold signal 16 can be a voltage input from any source, and can be controlled by the operator of the signal rectification and timing circuit 10. The lower threshold signal 16 can be selected to optimize the range between the nominal threshold 80 and the lower threshold signal 16 while minimizing the bounce of the second digital output signal 43.
[0032] The method still further includes the step 108 of inputting the variable amplitude input signal 12 and the upper threshold signal 14 into a first comparator 22.
The method also includes the step 110 of inputting the variable amplitude input signal and the lower threshold signal 16 into a second comparator 42.
[0033] The method also includes the step 112 of generating a first digital output signal 23 in the first comparator 22 using a hysteresis circuit. The method further includes the step 114 of generating a second digital output signal 43 in the second comparator 42 using a hysteresis circuit.
[0034] The method includes the step 116 of inputting the first logic input signal 60 and the second logic input signal 62 into a logic array 64. The first logic input signal 60 and the second logic input signal 62 are the resulting signals from the first digital output signal 23 of the first comparator 22 and the second digital output signal 43 of the second comparator 42 after conditioning by the hysteresis circuits.
[0035] The method further includes the step 118 of generating a digital level pulse output signal 70 in the logic array 64 that has a digital transition where the variable amplitude input signal 12 passed through the amplitude of the upper threshold signal 14. The transition may be precisely at the threshold crossing.
[0036] The signal rectification and timing circuit method and apparatus is one solution to eliminate excess propagation delay error and excess signal phase shift in a resultant output waveform created by some circuits using a single comparator to condition a variable amplitude input signal with an upper threshold level and a lower threshold level. Additionally, the signal rectification and timing circuit method and apparatus reduces the cost of generating a digital level pulse output signal with a transition precisely where the amplitude of the variable amplitude input signal crossed a threshold. Furthermore, the signal rectification and timing circuit method and apparatus reduces the need for bandwidth while generating a digital level pulse output signal with a transition precisely where the amplitude of the variable amplitude input signal crossed a threshold.
[0037] The invention has been described with reference to the example embodiments described above. Modifications and alterations will occur to others upon a reading and understanding of this specification. Example embodiments incorporating one or more aspects of the invention are intended to include all such modifications and alterations insofar as they come within the scope of the appended claims.
Claims (4)
1. Fremgangsmåde til rektificering af et elektronisk signal, hvilken fremgangsmåde omfatter trinnene: (a) generering af et variabelt amplitudeindgangssignal (12); (b) bestemmelse af et øvre tærskelniveau; (c) bestemmelse af et nedre tærskelniveau; (d) indlæsning af det variable amplitudeindgangssignal (12) og det øvre tærskelniveau i en første komparator (22); (e) indlæsning af det variable amplitudeindgangssignal (12) og det nedre tærskelniveau i en anden komparator (42); (f) generering af et første digitalt udgangssignal (23) i den første komparator (22) ved anvendelse af et første, eksternt hysteresekredsløb, som omfatter en første kondensator (28) og en første modstand (30), som styrer en AC-hysterese om indgangen af den første komparator (22) og desuden omfatter en anden modstand (32), som styrer en DC-hysterese om den første komparator (22), hvor det første digitale udgangssignal (23) udnyttes af det første eksterne hysteresekredsløb; (g) generering af et andet digitalt udgangssignal (43) i den anden komparator (42) ved anvendelse af et andet, eksternt hysteresekredsløb, som omfatter en anden kondensator (48) og en tredje modstand (50), som styrer en AC-hysterese om indgangen af den anden komparator (42) og desuden omfatter en fjerde modstand (52), som styrer en DC-hysterese om den anden komparator (42), hvor det andet digitale udgangssignal udnyttes af det andet hysteresekredsløb; (h) indlæsning af det første digitale udgangssignal (23) og det andet digitale udgangssignal (43) i en logisk array (64); og (i) generering af et digitalt niveaupulsudgangssignal (70) i den logiske array (64), som har en digital overgang, hvor det variable amplitudeindgangssignal (12) gik gennem en af den nedre tærskel og den øvre tærskel, hvor trinnet, hvor det første digitale udgangssignal (23) genereres i den første komparator (22) ved anvendelse af det første hysteresekredsløb, omfatter at sende det første digitale udgangssignal (23) til den første komparator (22) gennem kredsløbet indbefattende den anden modstand (32) og at sende det første digitale udgangssignal (23) til den øvre tærskeniveauindgang ind i kredsløbet af den første komparator (22) gennem kredsløbet indbefattende den første modstand (30) og den første kapacitans (28).
2. Fremgangsmåde ifølge krav 1, hvorved trinnet, hvor det andet digitale udgangssignal (43) genereres i den anden komparator (42) ved anvendelse af det andet hysteresekredsløb, omfatter at sende det andet digitale udgangssignal (43) til den anden komparator (42) gennem et kredsløb, som indbefatter den fjerde modstand (52), og at sende det andet digitale udgangssignal (43) til den nedre tærskelniveauindgang ind i det andet komparatorkredsløb gennem et kredsløb, der indbefatter den anden kapacitans (48) og den tredje modstand (50).
3. Signalrektificering og timing-kredsløb (10) til modtagelse af et variabelt amplitudeindgangssignal (12) og generering af et digitalt niveaupulsudgangssignal (70), som laver en overgang på det tidspunkt, hvor det variable amplitudeindgangssignal (12) går gennem et tærskelniveau, hvor rektificeringen og timing-kredsløbet (10) omfatter: (a) en første komparator (22) til sammenligning af det variable amplitudeindgangssignal (12) og et fastlagt øvre tærskelsignal (14) og generering af et første digitalt udgangssignal (23), der angiver sammenligningen; (b) et første, eksternt hysteresekredsløb, som er koblet til den første komparator (22), hvor det første digitale udgangssignal udnyttes af det første hysteresekredsløb; (c) en anden komparator (42) til sammenligning af det variable amplitudeindgangssignal (12) og et fastlagt nedre tærskelsignal (16) og generering af et andet digitalt udgangssignal (43), der angiver sammenligningen; (d) et andet, eksternt hysteresekredsløb, som er koblet til den anden komparator (42), hvor det andet digitale udgangssignal udnyttes af det andet hysteresekredsløb; og (e) en logisk array (64) til modtagelse af det første digitale udgangssignal (23) og det andet digitale udgangssignal (43) og generering af det digitale niveaupulsudgangssignal (70), som laver en overgang på det tidspunkt, hvor det variable amplitudeindgangssignal (12) går gennem en af den nedre tærskel og den øvre tærskel; hvor det første hysteresekredsløb omfatter en anden modstand (32), som sender det første digitale udgangssignal (23) til den første komparator (22) og desuden indbefatter en første kapacitans (28) og en første modstand (30), som sender det første digitale udgangssignal (23) til den øvre tærskelniveau-indgang ind i den første komparator (22).
4. Rektificering og timing-kredsløb ifølge krav 3, hvor det andet hysterese-kredsløb omfatter en fjerde modstand (52), som sender det første digitale udgangssignal (43) til den første komparator (22) og indbefatter en anden kapacitans (48) og en tredje modstand (50), som sender det andet digitale udgangssignal (43) til den øvre tærskelniveauindgang ind i den anden komparator (42).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201113170443 | 2011-06-28 | ||
| US13/170,443 US8519744B2 (en) | 2011-06-28 | 2011-06-28 | Method of utilizing dual comparators to facilitate a precision signal rectification and timing system without signal feedback |
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| Publication Number | Publication Date |
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| DK201270357A DK201270357A (en) | 2012-12-29 |
| DK178660B1 true DK178660B1 (da) | 2016-10-24 |
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| Country | Link |
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| US (1) | US8519744B2 (da) |
| JP (1) | JP2013034188A (da) |
| CN (1) | CN102882494A (da) |
| DE (1) | DE102012105559A1 (da) |
| DK (1) | DK178660B1 (da) |
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| CN102901902A (zh) * | 2011-07-28 | 2013-01-30 | 飞思卡尔半导体公司 | 半导体器件的并联电源连接的测试方法 |
| US9342485B2 (en) * | 2013-01-31 | 2016-05-17 | General Electric Company | Methods and systems for conditioning signals from a speed sensor |
| US11671286B2 (en) | 2018-12-12 | 2023-06-06 | Rambus Inc. | Live offset cancellation of the decision feedback equalization data slicers |
| US11005465B1 (en) * | 2020-01-13 | 2021-05-11 | Hamilton Sunstrand Corporation | Zero-cross circuit with low phase delay |
| CN114337614B (zh) * | 2021-12-07 | 2023-06-27 | 杭州加速科技有限公司 | 基于比较器的高精度边沿检测方法及系统 |
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- 2012-06-26 DE DE102012105559A patent/DE102012105559A1/de active Pending
- 2012-06-27 JP JP2012143961A patent/JP2013034188A/ja active Pending
- 2012-06-28 CN CN2012103414461A patent/CN102882494A/zh active Pending
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2013034188A (ja) | 2013-02-14 |
| DK201270357A (en) | 2012-12-29 |
| CN102882494A (zh) | 2013-01-16 |
| US20130002305A1 (en) | 2013-01-03 |
| DE102012105559A1 (de) | 2013-01-03 |
| US8519744B2 (en) | 2013-08-27 |
| DE102012105559A8 (de) | 2013-03-21 |
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