DE69826573D1 - Speicheranordnung die Burstaddressierung zum Lesen und Schreiben erlaubt durch einen einzigen Addresseneingang - Google Patents

Speicheranordnung die Burstaddressierung zum Lesen und Schreiben erlaubt durch einen einzigen Addresseneingang

Info

Publication number
DE69826573D1
DE69826573D1 DE69826573T DE69826573T DE69826573D1 DE 69826573 D1 DE69826573 D1 DE 69826573D1 DE 69826573 T DE69826573 T DE 69826573T DE 69826573 T DE69826573 T DE 69826573T DE 69826573 D1 DE69826573 D1 DE 69826573D1
Authority
DE
Germany
Prior art keywords
writing
reading
address input
arrangement allows
memory arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69826573T
Other languages
English (en)
Other versions
DE69826573T2 (de
Inventor
Atsushi - Takasugi
Takeshi Gotoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69826573D1 publication Critical patent/DE69826573D1/de
Publication of DE69826573T2 publication Critical patent/DE69826573T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
DE69826573T 1997-07-10 1998-05-27 Speicheranordnung die Burstaddressierung zum Lesen und Schreiben erlaubt durch einen einzigen Addresseneingang Expired - Lifetime DE69826573T2 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP18553297 1997-07-10
JP18553297 1997-07-10
JP21247497 1997-07-22
JP21247497 1997-07-22
JP13717198A JP3722619B2 (ja) 1997-07-10 1998-05-19 メモリ装置及びそのアクセス制御方法
JP13717198 1998-05-19

Publications (2)

Publication Number Publication Date
DE69826573D1 true DE69826573D1 (de) 2004-11-04
DE69826573T2 DE69826573T2 (de) 2005-11-17

Family

ID=27317416

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69826573T Expired - Lifetime DE69826573T2 (de) 1997-07-10 1998-05-27 Speicheranordnung die Burstaddressierung zum Lesen und Schreiben erlaubt durch einen einzigen Addresseneingang

Country Status (6)

Country Link
US (1) US5978303A (de)
EP (1) EP0890953B1 (de)
JP (1) JP3722619B2 (de)
KR (1) KR100336330B1 (de)
DE (1) DE69826573T2 (de)
TW (1) TW378320B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3201335B2 (ja) * 1998-03-17 2001-08-20 日本電気株式会社 メモリアドレス発生回路及び半導体記憶装置
JP3776295B2 (ja) 2000-06-26 2006-05-17 沖電気工業株式会社 シリアルアクセスメモリおよびデータライト／リード方法
JP3638857B2 (ja) 2000-06-26 2005-04-13 沖電気工業株式会社 シリアルアクセスメモリおよびデータライト／リード方法
FR2826226A1 (fr) * 2001-06-19 2002-12-20 Koninkl Philips Electronics Nv Circuit memoire concu pour un acces parallele en lecture ou en ecriture de donnees a plusieurs composantes
JP4310100B2 (ja) * 2002-11-29 2009-08-05 Ｏｋｉセミコンダクタ株式会社 フィールドメモリ
JP4099578B2 (ja) * 2002-12-09 2008-06-11 ソニー株式会社 半導体装置及び画像データ処理装置
US7486683B2 (en) * 2003-07-23 2009-02-03 International Business Machines Corporation Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's
US7002873B2 (en) * 2003-12-19 2006-02-21 Intel Corporation Memory array with staged output
KR100730689B1 (ko) * 2005-07-29 2007-06-21 엠텍비젼 주식회사 동영상 데이터 인코더 및 그 제어 방법
US8704743B2 (en) * 2008-09-30 2014-04-22 Apple Inc. Power savings technique for LCD using increased frame inversion rate
JP5314640B2 (ja) * 2010-06-21 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置
US9082200B2 (en) * 2012-12-04 2015-07-14 Siemens Medical Solutions Usa, Inc. System for histogram computation
TWI518666B (zh) * 2013-03-05 2016-01-21 友達光電股份有限公司 顯示裝置及其共同電壓產生電路
FR3015068B1 (fr) * 2013-12-18 2016-01-01 Commissariat Energie Atomique Module de traitement du signal, notamment pour reseau de neurones et circuit neuronal
CN108701077B (zh) 2016-05-03 2023-11-10 拉姆伯斯公司 具有高效写入操作的存储器组件
KR102430080B1 (ko) 2019-06-04 2022-08-04 경북대학교 산학협력단 메틸 갈레이트 및 틸로신을 포함하는 항균용 조성물

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2724932B2 (ja) * 1991-12-03 1998-03-09 三菱電機株式会社 デュアルポートメモリ
US5377154A (en) * 1992-01-31 1994-12-27 Oki Electric Industry Co., Ltd. Multiple serial-access memory
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
JP3666671B2 (ja) * 1994-12-20 2005-06-29 株式会社日立製作所 半導体装置
JP3223817B2 (ja) * 1996-11-08 2001-10-29 日本電気株式会社 半導体メモリ装置及びその駆動方法

Also Published As

Publication number Publication date
EP0890953A3 (de) 1999-11-24
EP0890953B1 (de) 2004-09-29
KR19990013597A (ko) 1999-02-25
JPH1196748A (ja) 1999-04-09
DE69826573T2 (de) 2005-11-17
KR100336330B1 (ko) 2002-09-27
EP0890953A2 (de) 1999-01-13
TW378320B (en) 2000-01-01
US5978303A (en) 1999-11-02
JP3722619B2 (ja) 2005-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: GROSSE, SCHUMACHER, KNAUER, VON HIRSCHHAUSEN, 8033

8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP