DE69620934D1 - Schreibschaltung für einen synchronen RAM Speicher - Google Patents

Schreibschaltung für einen synchronen RAM Speicher

Info

Publication number
DE69620934D1
DE69620934D1 DE69620934T DE69620934T DE69620934D1 DE 69620934 D1 DE69620934 D1 DE 69620934D1 DE 69620934 T DE69620934 T DE 69620934T DE 69620934 T DE69620934 T DE 69620934T DE 69620934 D1 DE69620934 D1 DE 69620934D1
Authority
DE
Germany
Prior art keywords
ram memory
write circuit
synchronous ram
synchronous
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69620934T
Other languages
English (en)
Other versions
DE69620934T2 (de
Inventor
Philip M Freidin
Edmond Y Cheung
Charles R Erickson
Tsung-Lu Syu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of DE69620934D1 publication Critical patent/DE69620934D1/de
Application granted granted Critical
Publication of DE69620934T2 publication Critical patent/DE69620934T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
DE69620934T 1995-02-10 1996-02-09 Schreibschaltung für einen synchronen RAM Speicher Expired - Lifetime DE69620934T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/386,972 US5566123A (en) 1995-02-10 1995-02-10 Synchronous dual port ram

Publications (2)

Publication Number Publication Date
DE69620934D1 true DE69620934D1 (de) 2002-06-06
DE69620934T2 DE69620934T2 (de) 2002-11-21

Family

ID=23527868

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620934T Expired - Lifetime DE69620934T2 (de) 1995-02-10 1996-02-09 Schreibschaltung für einen synchronen RAM Speicher

Country Status (4)

Country Link
US (2) US5566123A (de)
EP (2) EP0726577B1 (de)
JP (1) JP3868531B2 (de)
DE (1) DE69620934T2 (de)

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Also Published As

Publication number Publication date
EP1154435A3 (de) 2004-02-04
EP0726577B1 (de) 2002-05-02
US5566123A (en) 1996-10-15
EP0726577A2 (de) 1996-08-14
JP3868531B2 (ja) 2007-01-17
DE69620934T2 (de) 2002-11-21
EP1154435B1 (de) 2015-08-26
EP1154435A2 (de) 2001-11-14
JPH08263984A (ja) 1996-10-11
EP0726577A3 (de) 1998-11-25
US5631577A (en) 1997-05-20

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