DE3865312D1 - Leseschaltung fuer einen speicher. - Google Patents

Leseschaltung fuer einen speicher.

Info

Publication number
DE3865312D1
DE3865312D1 DE8888400162T DE3865312T DE3865312D1 DE 3865312 D1 DE3865312 D1 DE 3865312D1 DE 8888400162 T DE8888400162 T DE 8888400162T DE 3865312 T DE3865312 T DE 3865312T DE 3865312 D1 DE3865312 D1 DE 3865312D1
Authority
DE
Germany
Prior art keywords
memory
reading circuit
reading
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888400162T
Other languages
English (en)
Inventor
Jacek Antoni Kowalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE3865312D1 publication Critical patent/DE3865312D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
DE8888400162T 1987-01-27 1988-01-26 Leseschaltung fuer einen speicher. Expired - Lifetime DE3865312D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8700931A FR2610134B1 (fr) 1987-01-27 1987-01-27 Circuit de lecture pour memoire

Publications (1)

Publication Number Publication Date
DE3865312D1 true DE3865312D1 (de) 1991-11-14

Family

ID=9347305

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888400162T Expired - Lifetime DE3865312D1 (de) 1987-01-27 1988-01-26 Leseschaltung fuer einen speicher.

Country Status (5)

Country Link
US (1) US4896298A (de)
EP (1) EP0278832B1 (de)
JP (1) JP2588485B2 (de)
DE (1) DE3865312D1 (de)
FR (1) FR2610134B1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5153854A (en) * 1989-08-18 1992-10-06 Motorola, Inc. EEPROM memory system having selectable programming voltage for low power readability
WO1991003054A1 (en) * 1989-08-18 1991-03-07 Motorola, Inc. Memory cell
JP3060680B2 (ja) * 1990-11-30 2000-07-10 日本電気株式会社 不揮発性半導体記憶装置
FR2690008B1 (fr) * 1991-05-29 1994-06-10 Gemplus Card Int Memoire avec cellule memoire eeprom a effet capacitif et procede de lecture d'une telle cellule memoire.
JP2637314B2 (ja) * 1991-08-30 1997-08-06 株式会社東芝 不揮発性メモリ回路
FR2683342B1 (fr) * 1991-10-31 1994-01-07 Gemplus Card International Circuit d'interface pour carte a circuit integre.
FR2686989B1 (fr) * 1992-01-30 1997-01-17 Gemplus Card Int Procede de comptage de securite pour un compteur electronique binaire.
FR2703501B1 (fr) * 1993-04-01 1995-05-19 Gemplus Card Int Circuit intégré pour carte à mémoire et procédé de décomptage d'unités dans une carte à mémoire.
FR2703526B1 (fr) * 1993-04-02 1995-05-19 Gemplus Card Int Circuit de déclenchement automatique.
FR2705810B1 (fr) * 1993-05-26 1995-06-30 Gemplus Card Int Puce de carte à puce munie d'un moyen de limitation du nombre d'authentifications.
US7480183B2 (en) * 2006-07-05 2009-01-20 Panasonic Corporation Semiconductor memory device, and read method and read circuit for the same
US9093141B2 (en) 2011-12-16 2015-07-28 Intermec Ip Corp. Phase change memory devices, method for encoding, and methods for storing data
KR102580945B1 (ko) * 2016-11-17 2023-09-20 삼성전자주식회사 디커플링 회로를 포함하는 비휘발성 메모리 장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS601712B2 (ja) * 1980-12-04 1985-01-17 株式会社東芝 半導体記憶装置
US4545038A (en) * 1982-04-05 1985-10-01 Texas Instruments Incorporated Precharged discharge sensing for EPROM

Also Published As

Publication number Publication date
FR2610134A1 (fr) 1988-07-29
EP0278832B1 (de) 1991-10-09
FR2610134B1 (fr) 1989-03-31
JPS63195899A (ja) 1988-08-12
EP0278832A3 (en) 1988-09-07
JP2588485B2 (ja) 1997-03-05
EP0278832A2 (de) 1988-08-17
US4896298A (en) 1990-01-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition