WO1991003054A1 - Memory cell - Google Patents

Memory cell Download PDF

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Publication number
WO1991003054A1
WO1991003054A1 PCT/US1990/004192 US9004192W WO9103054A1 WO 1991003054 A1 WO1991003054 A1 WO 1991003054A1 US 9004192 W US9004192 W US 9004192W WO 9103054 A1 WO9103054 A1 WO 9103054A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
terminal
data
programming
write
Prior art date
Application number
PCT/US1990/004192
Other languages
French (fr)
Inventor
Barry Wayne Herold
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1991003054A1 publication Critical patent/WO1991003054A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • This invention relates in general to semiconductor memories and more particularly to electrically erasable programmable semiconductor memories.
  • Electrically erasable programmable semiconductor memories are well known.
  • the electrically erasable programmable read only memory (EEPROM) was developed to provide an easily alterable, non-volatile storage method for digital data.
  • MOS metal oxide semiconductor
  • a programming voltage must be applied to a selected EEPROM storage cell after the EEPROM is write enabled.
  • the EEPROM programming voltage can be supplied externally or generated internally from a lower external voltage supply by a voltage multiplier.
  • Digital data to be stored by the EEPROM typically is written to the storage cell using a Vpp voltage supply of 25 volts DC, V ⁇ 3d voltage supply of 5 volts DC, and V ss voltage supply of 0 volts DC.
  • Vdd and V ss voltage supplies are used to represent logical data values of true and false or "1" and "0", respectively, when providing data to the EEPROM in either a serial bit stream or parallel word format.
  • Storage of digital data into EEPROM memory cells is determined by the addressing and bit organization hardware in the EEPROM.
  • Current MOS technology used in EEPROM devices dictates that a programming voltage of 25 volts DC must be applied to the memory element, a floating gate field effect transistor, in the proper manner to either trap (write) or remove (erase) electrical charge from the floating gate. During programming, the programming voltage is applied via the row and column decoder circuitry to the memory cell.
  • a circuit architecture for a memory system comprising a row decoder for selectively supplying first, second, third and programming voltages, a column decoder for selectively providing the third and programming voltages, a plurality of memory cells each uniquely coupled between the row decoder and the column decoder, data being written into a cell when the programming voltage and the third voltage is applied from the row decoder and the third voltage is applied from the column decoder, data being read from the cell when the first voltage is applied by the row decoder and the third voltage is applied by the column decoder, data being read from the cell when the second voltage is applied by the row decoder and the third voltage is applied by the column decoder, and data being erased from the cell when the programming voltage and the third voltage is applied by the row decoder and column decoder.
  • FIG. 1 is a block diagram of a prior art EEPROM memory system.
  • FIG. 2 is a block diagram of the EEPROM memory system in accordance with the preferred embodiment.
  • FIG. 3 is a schematic of a memory cell in accordance with the preferred embodiment.
  • the prior art EEPROM architecture shown comprises row decoders 101 and column decoders 102 having three input voltages, pp (programming voltage, typically 25 volts DC) , V d (drain voltage, typically 5 volts DC) , and V ss (source voltage, typically 0 volts DC) .
  • the V d and V ss voltages are used to couple data, address, and control signals to and from peripheral devices (i.e. microprocessors, direct memory access controllers) and the core memory 103.
  • the Vpp supply is only required internal to the EEPROM device for programming the memory cell.
  • All presently known EEPROM memory systems must leave the programming voltage generator 104 running or generate an intermediate voltage to provide bias for the row and column decoders 101, 102, because the row and column decoders 101, 102, have integrated the high voltage programming circuitry with the low voltage interface circuitry.
  • level shifting and breakdown protection circuitry must be included to prevent the high voltage from destroying devices in the low voltage sections. The fact that the programming voltage generator 104 is left on during all modes of operation wastes power.
  • the preferred embodiment of the memory system has row decoders 201 for selectively supplying first, second, third, and programming voltages to the core memory 203, column decoders 202 for selectively providing third and programming voltages to the core memory 203, and a core memory 203 comprised of a plurality of memory cells each uniquely coupled between the row and column decoders 201, 202.
  • the preferred magnitude for the first, second, third, and programming voltages are 0.0, 1.0, 3.0, and 25.0 volts DC, respectively.
  • the first, second, and third voltages are used to couple data, address, and control signals to and from peripheral devices (i.e. microprocessors, direct memory access controllers) , the core memory 203, and programming voltage generator 208.
  • the high voltage 204, 205, and low voltage 206, 207, sections in the row decoders 201 and column decoders 202 are separate in the preferred embodiment. Since the read mode requires only the low voltage sections 206, 207, the controller will shut down the programming voltage generator 208 during read mode operation yielding a system power savings.
  • the preferred embodiment of the EEPROM memory cell comprises a data terminal capable of receiving and transmitting data, a read enable terminal capable of receiving one of the first, second, and third voltages, a write/erase terminal capable of receiving one of the programming voltage and the third voltage, the program enable terminal capable of receiving one of the programming voltage and the third voltage, a current drain terminal, a first field effect transistor 301 having its drain-source current path coupled between a data terminal and a node 302, and a gate coupled to a write/erase terminal, a second field effect transistor 303 having its drain-source current path coupled between a data terminal and a node 302, and a gate coupled to a read enable terminal, and a floating gate field effect transistor 304 having its drain-source current path coupled between a node 302 and a current drain terminal, and a gate coupled to a program enable terminal.
  • Data from the data terminal is written into the memory cell when the programming voltage is applied to the write/erase terminal and the third voltage is applied to the read enable and program enable terminals.
  • Data is read from the data terminal when the first voltage is applied to the read enable terminal and the third voltage is applied to the write/erase, program enable, and current drain terminals.
  • Data is read from the data terminal when the second voltage is applied the read enable terminal and the third voltage is applied to the write/erase, program enable, and current drain terminals.
  • Data is erased from the memory cell when the programming voltage is applied to the write/erase and program enable terminals and the third voltage is applied to the read enable, data, and current drain terminals.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

A memory system for the non-volatile storage of digital information. The digital storage element is a semiconductor memory cell (304) which is electrically erasable (301), readable (303), and programmable (301, 304). There is a low voltage (206, 207) read mode provided to decrease system power requirements.

Description

MEMORY CELL
Field of the Invention
This invention relates in general to semiconductor memories and more particularly to electrically erasable programmable semiconductor memories.
Background of the Invention
Electrically erasable programmable semiconductor memories are well known. The electrically erasable programmable read only memory (EEPROM) was developed to provide an easily alterable, non-volatile storage method for digital data. In order to program a MOS (metal oxide semiconductor) EEPROM device, a programming voltage must be applied to a selected EEPROM storage cell after the EEPROM is write enabled. The EEPROM programming voltage can be supplied externally or generated internally from a lower external voltage supply by a voltage multiplier. Digital data to be stored by the EEPROM typically is written to the storage cell using a Vpp voltage supply of 25 volts DC, V<3d voltage supply of 5 volts DC, and Vss voltage supply of 0 volts DC. The Vdd and Vss voltage supplies are used to represent logical data values of true and false or "1" and "0", respectively, when providing data to the EEPROM in either a serial bit stream or parallel word format. Storage of digital data into EEPROM memory cells is determined by the addressing and bit organization hardware in the EEPROM. Current MOS technology used in EEPROM devices dictates that a programming voltage of 25 volts DC must be applied to the memory element, a floating gate field effect transistor, in the proper manner to either trap (write) or remove (erase) electrical charge from the floating gate. During programming, the programming voltage is applied via the row and column decoder circuitry to the memory cell. Because existing row and column decoder circuitry must provide an interface for the VDD and VSS voltages as well as the programming voltage, complex level shifting and breakdown protection topologies must be employed to prevent the cell from being re-programmed or erased during normal memory read access. This requirement increases complexity, reduces reliability, and increases the cost of the EEPROM. Another constraint imposed by the need for level shifting circuitry and the higher VDD voltage bias required to allow this circuitry to function properly is that existing EEPROM1s cannot be read below a VDD supply voltage of approximately 3.0 volts.
Thus, what is needed is a low power EEPROM circuit architecture capable of being read at a lower voltage.
Summary of the Invention
Accordingly, it is an object of the present invention to provide an improved EEPROM cell. In carrying out the above and other objects of the invention in one form, there is provided a circuit architecture for a memory system comprising a row decoder for selectively supplying first, second, third and programming voltages, a column decoder for selectively providing the third and programming voltages, a plurality of memory cells each uniquely coupled between the row decoder and the column decoder, data being written into a cell when the programming voltage and the third voltage is applied from the row decoder and the third voltage is applied from the column decoder, data being read from the cell when the first voltage is applied by the row decoder and the third voltage is applied by the column decoder, data being read from the cell when the second voltage is applied by the row decoder and the third voltage is applied by the column decoder, and data being erased from the cell when the programming voltage and the third voltage is applied by the row decoder and column decoder. Brief Description of the Drawings
FIG. 1 is a block diagram of a prior art EEPROM memory system. FIG. 2 is a block diagram of the EEPROM memory system in accordance with the preferred embodiment.
FIG. 3 is a schematic of a memory cell in accordance with the preferred embodiment.
Description of a Preferred Embodiment
Referring to FIG. 1, the prior art EEPROM architecture shown comprises row decoders 101 and column decoders 102 having three input voltages, pp (programming voltage, typically 25 volts DC) , V d (drain voltage, typically 5 volts DC) , and Vss (source voltage, typically 0 volts DC) . The V d and Vss voltages are used to couple data, address, and control signals to and from peripheral devices (i.e. microprocessors, direct memory access controllers) and the core memory 103. The Vpp supply is only required internal to the EEPROM device for programming the memory cell. All presently known EEPROM memory systems must leave the programming voltage generator 104 running or generate an intermediate voltage to provide bias for the row and column decoders 101, 102, because the row and column decoders 101, 102, have integrated the high voltage programming circuitry with the low voltage interface circuitry. By integrating the high and low voltage sections of the decoders, level shifting and breakdown protection circuitry must be included to prevent the high voltage from destroying devices in the low voltage sections. The fact that the programming voltage generator 104 is left on during all modes of operation wastes power.
Referring to FIG. 2, the preferred embodiment of the memory system has row decoders 201 for selectively supplying first, second, third, and programming voltages to the core memory 203, column decoders 202 for selectively providing third and programming voltages to the core memory 203, and a core memory 203 comprised of a plurality of memory cells each uniquely coupled between the row and column decoders 201, 202. The preferred magnitude for the first, second, third, and programming voltages are 0.0, 1.0, 3.0, and 25.0 volts DC, respectively. The first, second, and third voltages are used to couple data, address, and control signals to and from peripheral devices (i.e. microprocessors, direct memory access controllers) , the core memory 203, and programming voltage generator 208. The high voltage 204, 205, and low voltage 206, 207, sections in the row decoders 201 and column decoders 202 are separate in the preferred embodiment. Since the read mode requires only the low voltage sections 206, 207, the controller will shut down the programming voltage generator 208 during read mode operation yielding a system power savings.
Referring to FIG. 3, the preferred embodiment of the EEPROM memory cell comprises a data terminal capable of receiving and transmitting data, a read enable terminal capable of receiving one of the first, second, and third voltages, a write/erase terminal capable of receiving one of the programming voltage and the third voltage, the program enable terminal capable of receiving one of the programming voltage and the third voltage, a current drain terminal, a first field effect transistor 301 having its drain-source current path coupled between a data terminal and a node 302, and a gate coupled to a write/erase terminal, a second field effect transistor 303 having its drain-source current path coupled between a data terminal and a node 302, and a gate coupled to a read enable terminal, and a floating gate field effect transistor 304 having its drain-source current path coupled between a node 302 and a current drain terminal, and a gate coupled to a program enable terminal. Data from the data terminal is written into the memory cell when the programming voltage is applied to the write/erase terminal and the third voltage is applied to the read enable and program enable terminals. Data is read from the data terminal when the first voltage is applied to the read enable terminal and the third voltage is applied to the write/erase, program enable, and current drain terminals. Data is read from the data terminal when the second voltage is applied the read enable terminal and the third voltage is applied to the write/erase, program enable, and current drain terminals. Data is erased from the memory cell when the programming voltage is applied to the write/erase and program enable terminals and the third voltage is applied to the read enable, data, and current drain terminals.

Claims

1. A memory system comprising: a plurality of memory cells; and decoder means for writing, reading, and programming each of said memory cells uniquely coupled thereto by supplying write, read, and programming voltages respectively, thereto, the write voltage being multiplied for generating the programming voltage only when at least one of the cells is being programmed.
2. A memory system comprising: row decoder means for selectively supplying first, second, third and programming voltages; column decoder means for selectively providing said third and programming voltages; and a plurality of memory cells each uniquely coupled between said row decoder means and said column decoder means, data being written into said cell when said programming voltage and the third voltage is applied from said row decoder and said third voltage is applied from said column decoder, data being read from said cell when said first voltage is applied by said row decoder and said third voltage is applied by said column decoder, data being read from said cell when said second voltage is applied by said row decoder and said third voltage is applied by said column decoder, and data being erased from said cell when said programming voltage and said third voltage is applied by said row decoder and said column decoder.
3. The memory system according to claim 2 wherein said first voltage, second voltage, and programming voltage have magnitudes greater than said third voltage.
4. The memory system according to claim 2 wherein said programming voltage has a magnitude substantially greater than said first voltage, second voltage, and third voltage, and said programming voltage is generated by multiplying said first voltage.
5. The memory system according to claim 2 wherein said first voltage has a magnitude greater than said second voltage.
6. The memory system according to claim 2 wherein said programming, first, second, and third voltages have decreasing magnitudes, respectively.
7. The memory system according to claim 2 wherein said memory cells comprise: a data terminal capable of receiving and transmitting data; a read enable terminal capable of receiving one of said first, second, and third voltages; a write/erase terminal capable of receiving one of said programming voltage and said third voltage; a program enable terminal capable of receiving one of said programming voltage and said third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain- source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal.
8. An electrically erasable programmable memory cell comprising: a data terminal capable of receiving and transmitting data; a read enable terminal capable of receiving one of a first, second, and third voltages; a write/erase terminal capable of receiving one of a programming voltage and a third voltage; a program enable terminal capable of receiving one of a programming voltage and a third voltage; a current drain terminal; a first field effect transistor having its drain-source current path coupled between said data terminal and a node, and a gate coupled to said write/erase terminal; a second field effect transistor having its drain- source current path coupled between said data terminal and said node, and a gate coupled to said read enable terminal; and a floating gate field effect transistor having its drain-source current path coupled between said node and said current drain terminal, and a gate coupled to said program enable terminal, whereby data from said data terminal is written into said cell when the programming voltage is applied to said write/erase terminal and said third voltage is applied to said read enable and program enable terminals, data is read from said data terminal when said first voltage is applied to said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, data is read from said data terminal when said second voltage is applied said read enable terminal and said third voltage is applied to said write/erase, program enable, and current drain terminals, and data is erased from said cell when said programming voltage is applied to said write/erase and program enable terminals and said third voltage is applied to said read enable, data, and current drain terminals.
9. The memory system according to claim 8 wherein said first voltage, second voltage, and programming voltage have magnitudes greater than said third voltage.
10. The memory system according to claim 8 wherein said programming voltage has a magnitude substantially greater than said first voltage, second voltage, and third voltage, and said programming voltage is generated by multiplying said first voltage.
11. The memory system according to claim 8 wherein said first voltage has a magnitude greater than said second voltage.
PCT/US1990/004192 1989-08-18 1990-07-27 Memory cell WO1991003054A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39583489A 1989-08-18 1989-08-18
US395,834 1989-08-18

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WO1991003054A1 true WO1991003054A1 (en) 1991-03-07

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0736876A1 (en) * 1995-04-04 1996-10-09 STMicroelectronics S.r.l. Selective fuse encoder
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775958A (en) * 1985-06-26 1988-10-04 Nec Corporation Semiconductor memory system
US4829203A (en) * 1988-04-20 1989-05-09 Texas Instruments Incorporated Integrated programmable bit circuit with minimal power requirement
US4855955A (en) * 1988-04-08 1989-08-08 Seeq Technology, Inc. Three transistor high endurance eeprom cell
US4858187A (en) * 1988-02-01 1989-08-15 Texas Instruments Incorporated Programming implementation circuit
US4896298A (en) * 1987-01-27 1990-01-23 Sgs-Thomson Microelectronics Sa Read circuit for memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775958A (en) * 1985-06-26 1988-10-04 Nec Corporation Semiconductor memory system
US4896298A (en) * 1987-01-27 1990-01-23 Sgs-Thomson Microelectronics Sa Read circuit for memory
US4858187A (en) * 1988-02-01 1989-08-15 Texas Instruments Incorporated Programming implementation circuit
US4855955A (en) * 1988-04-08 1989-08-08 Seeq Technology, Inc. Three transistor high endurance eeprom cell
US4829203A (en) * 1988-04-20 1989-05-09 Texas Instruments Incorporated Integrated programmable bit circuit with minimal power requirement

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0736876A1 (en) * 1995-04-04 1996-10-09 STMicroelectronics S.r.l. Selective fuse encoder
US5850361A (en) * 1995-04-04 1998-12-15 Sgs-Thomson Microelectronics S.R.L. Programmable memory with single bit encoding
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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