DE69809096D1 - Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher - Google Patents

Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher

Info

Publication number
DE69809096D1
DE69809096D1 DE69809096T DE69809096T DE69809096D1 DE 69809096 D1 DE69809096 D1 DE 69809096D1 DE 69809096 T DE69809096 T DE 69809096T DE 69809096 T DE69809096 T DE 69809096T DE 69809096 D1 DE69809096 D1 DE 69809096D1
Authority
DE
Germany
Prior art keywords
flop
circuit device
latch circuit
data latch
dram memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69809096T
Other languages
English (en)
Other versions
DE69809096T2 (de
Inventor
Takeshi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69809096D1 publication Critical patent/DE69809096D1/de
Publication of DE69809096T2 publication Critical patent/DE69809096T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
DE69809096T 1997-02-27 1998-02-26 Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher Expired - Lifetime DE69809096T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9044126A JP3062110B2 (ja) 1997-02-27 1997-02-27 データラッチ回路

Publications (2)

Publication Number Publication Date
DE69809096D1 true DE69809096D1 (de) 2002-12-12
DE69809096T2 DE69809096T2 (de) 2003-07-24

Family

ID=12682926

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69809096T Expired - Lifetime DE69809096T2 (de) 1997-02-27 1998-02-26 Datenverriegelungs-Schaltungsvorrichtung mit synchronem Halbleiterflipflop-DRAM-Speicher

Country Status (5)

Country Link
US (1) US5889709A (de)
EP (1) EP0862269B1 (de)
JP (1) JP3062110B2 (de)
KR (1) KR100258418B1 (de)
DE (1) DE69809096T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3368815B2 (ja) * 1997-11-10 2003-01-20 日本電気株式会社 フリップフロップ回路
KR100280435B1 (ko) * 1998-01-23 2001-02-01 김영환 엠씨유의파워노이즈방지회로
US6271715B1 (en) * 1998-02-27 2001-08-07 Maxim Integrated Products, Inc. Boosting circuit with supply-dependent gain
JP2000036192A (ja) * 1998-07-17 2000-02-02 Fujitsu Ltd 半導体集積回路
US6275086B1 (en) 1998-11-19 2001-08-14 Fujitsu Limited Clock signal generator for an integrated circuit
JP4253383B2 (ja) * 1998-12-14 2009-04-08 富士通マイクロエレクトロニクス株式会社 メモリ装置
TWI237802B (en) 2000-07-31 2005-08-11 Semiconductor Energy Lab Driving method of an electric circuit
EP1187327A1 (de) * 2000-09-04 2002-03-13 Infineon Technologies AG Flankengesteuerte D-Flipflop Schaltung
JP2002091604A (ja) * 2000-09-19 2002-03-29 Mitsubishi Electric Corp クロック発生回路
US7081780B2 (en) * 2004-06-01 2006-07-25 Randall Don Briggs Reset circuitry for an integrated circuit
US7131092B2 (en) * 2004-12-21 2006-10-31 Via Technologies, Inc. Clock gating circuit
KR100649973B1 (ko) * 2005-09-14 2006-11-27 주식회사 하이닉스반도체 내부 전압 발생 장치
WO2010064888A1 (en) * 2008-12-04 2010-06-10 Telekom Malaysia Berhad A frequency divider
US8890588B2 (en) * 2013-03-28 2014-11-18 Texas Instruments Incorporated Circuits and methods for asymmetric aging prevention
JP7035361B2 (ja) * 2017-07-28 2022-03-15 富士通株式会社 記憶装置、レジスタファイル回路及び記憶装置の制御方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4815041A (en) * 1987-03-19 1989-03-21 American Telephone And Telegraph Company Current surge elimination for CMOS devices
US4982116A (en) * 1989-12-26 1991-01-01 Linear Technology Corporation Clock selection circuit
JPH05327422A (ja) * 1992-05-22 1993-12-10 Nippon Steel Corp Ｄフリップフロップ回路
US5369377A (en) * 1993-10-13 1994-11-29 Zilog, Inc. Circuit for automatically detecting off-chip, crystal or on-chip, RC oscillator option
US5801561A (en) * 1995-05-01 1998-09-01 Intel Corporation Power-on initializing circuit
US5559458A (en) * 1995-05-11 1996-09-24 Lucent Technologies Inc. Reset circuit for a pipelined signal processor

Also Published As

Publication number Publication date
EP0862269A2 (de) 1998-09-02
JPH10242807A (ja) 1998-09-11
EP0862269A3 (de) 2000-11-22
KR100258418B1 (ko) 2000-06-01
EP0862269B1 (de) 2002-11-06
JP3062110B2 (ja) 2000-07-10
KR19980071570A (ko) 1998-10-26
DE69809096T2 (de) 2003-07-24
US5889709A (en) 1999-03-30

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

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