DE69724848D1 - Integrierte Halbleiterschaltung mit verbesserter Eingangspfadverkabelung - Google Patents

Integrierte Halbleiterschaltung mit verbesserter Eingangspfadverkabelung

Info

Publication number
DE69724848D1
DE69724848D1 DE69724848T DE69724848T DE69724848D1 DE 69724848 D1 DE69724848 D1 DE 69724848D1 DE 69724848 T DE69724848 T DE 69724848T DE 69724848 T DE69724848 T DE 69724848T DE 69724848 D1 DE69724848 D1 DE 69724848D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated semiconductor
input path
improved input
path cabling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69724848T
Other languages
English (en)
Other versions
DE69724848T2 (de
Inventor
Katsushi Nagaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69724848D1 publication Critical patent/DE69724848D1/de
Publication of DE69724848T2 publication Critical patent/DE69724848T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69724848T 1996-01-31 1997-01-30 Integrierte Halbleiterschaltung mit verbesserter Eingangspfadverkabelung Expired - Fee Related DE69724848T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1565796 1996-01-31
JP1565796 1996-01-31

Publications (2)

Publication Number Publication Date
DE69724848D1 true DE69724848D1 (de) 2003-10-23
DE69724848T2 DE69724848T2 (de) 2004-07-08

Family

ID=11894812

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724848T Expired - Fee Related DE69724848T2 (de) 1996-01-31 1997-01-30 Integrierte Halbleiterschaltung mit verbesserter Eingangspfadverkabelung

Country Status (5)

Country Link
US (1) US5724281A (de)
EP (1) EP0788109B1 (de)
KR (1) KR100244824B1 (de)
DE (1) DE69724848T2 (de)
TW (1) TW325566B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0818787A3 (de) * 1996-07-11 1999-08-25 Texas Instruments Inc. Verbesserungen betreffend Halbleiteranordnungen
JP3408479B2 (ja) * 1999-12-17 2003-05-19 日本電気株式会社 半導体記憶装置
JP2001283590A (ja) * 2000-03-31 2001-10-12 Fujitsu Ltd 半導体集積回路
JP2002176153A (ja) * 2000-12-05 2002-06-21 Fujitsu Ltd 半導体記憶装置
KR100852187B1 (ko) 2007-01-25 2008-08-13 삼성전자주식회사 효과적인 시스템 인 패키지 구성을 위한 핀 구성 변경 회로

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217917A (en) * 1990-03-20 1993-06-08 Hitachi, Ltd. Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
EP0476282A3 (en) * 1990-07-31 1992-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuits
JPH04157695A (ja) * 1990-10-19 1992-05-29 Sanyo Electric Co Ltd 半導体記憶装置
JPH0582746A (ja) * 1991-09-20 1993-04-02 Fujitsu Ltd 半導体記憶装置
US5353250A (en) * 1991-12-09 1994-10-04 Texas Instruments Inc. Pin programmable dram that provides customer option programmability
JP3218103B2 (ja) * 1992-12-25 2001-10-15 三菱電機株式会社 半導体記憶装置
US5471157A (en) * 1994-03-31 1995-11-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit with centralized control of edge transition detection pulse generation
JPH07312100A (ja) * 1994-05-17 1995-11-28 Seiko Instr Inc 半導体メモリ集積回路

Also Published As

Publication number Publication date
DE69724848T2 (de) 2004-07-08
US5724281A (en) 1998-03-03
EP0788109B1 (de) 2003-09-17
EP0788109A2 (de) 1997-08-06
KR970060520A (ko) 1997-08-12
KR100244824B1 (ko) 2000-02-15
EP0788109A3 (de) 1999-10-27
TW325566B (en) 1998-01-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee