DE69712562T2 - Halbleiteranordnung mit einem auf einen Träger gelöteten Chip mit Durchgangsleitungen und Herstellungsverfahren dafür - Google Patents
Halbleiteranordnung mit einem auf einen Träger gelöteten Chip mit Durchgangsleitungen und Herstellungsverfahren dafürInfo
- Publication number
- DE69712562T2 DE69712562T2 DE69712562T DE69712562T DE69712562T2 DE 69712562 T2 DE69712562 T2 DE 69712562T2 DE 69712562 T DE69712562 T DE 69712562T DE 69712562 T DE69712562 T DE 69712562T DE 69712562 T2 DE69712562 T2 DE 69712562T2
- Authority
- DE
- Germany
- Prior art keywords
- layer
- substrate
- line
- opening
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/014—Solder alloys
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Die Bonding (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9602492 | 1996-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69712562D1 DE69712562D1 (de) | 2002-06-20 |
| DE69712562T2 true DE69712562T2 (de) | 2002-12-19 |
Family
ID=9489670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69712562T Expired - Fee Related DE69712562T2 (de) | 1996-02-28 | 1997-02-19 | Halbleiteranordnung mit einem auf einen Träger gelöteten Chip mit Durchgangsleitungen und Herstellungsverfahren dafür |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5844321A (enExample) |
| EP (1) | EP0793269B1 (enExample) |
| JP (1) | JP4117042B2 (enExample) |
| DE (1) | DE69712562T2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3724110B2 (ja) | 1997-04-24 | 2005-12-07 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US20080099537A1 (en) * | 2006-10-31 | 2008-05-01 | Raytheon Company | Method for sealing vias in a substrate |
| DE102009028037A1 (de) * | 2009-07-27 | 2011-02-03 | Robert Bosch Gmbh | Bauelement mit einer elektrischen Durchkontaktierung, Verfahren zur Herstellung eines Bauelementes und Bauelementsystem |
| US9576873B2 (en) * | 2011-12-14 | 2017-02-21 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with routable trace and method of manufacture thereof |
| JP7168280B2 (ja) * | 2018-06-26 | 2022-11-09 | 住友電工デバイス・イノベーション株式会社 | 半導体装置、および、半導体チップの搭載方法 |
| US10861792B2 (en) * | 2019-03-25 | 2020-12-08 | Raytheon Company | Patterned wafer solder diffusion barrier |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02162735A (ja) * | 1988-12-15 | 1990-06-22 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| US5027189A (en) * | 1990-01-10 | 1991-06-25 | Hughes Aircraft Company | Integrated circuit solder die-attach design and method |
| FR2665574B1 (fr) * | 1990-08-03 | 1997-05-30 | Thomson Composants Microondes | Procede d'interconnexion entre un circuit integre et un circuit support, et circuit integre adapte a ce procede. |
| US5350662A (en) * | 1992-03-26 | 1994-09-27 | Hughes Aircraft Company | Maskless process for forming refractory metal layer in via holes of GaAs chips |
| US5635762A (en) * | 1993-05-18 | 1997-06-03 | U.S. Philips Corporation | Flip chip semiconductor device with dual purpose metallized ground conductor |
| JP3350152B2 (ja) | 1993-06-24 | 2002-11-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
-
1997
- 1997-02-19 EP EP97200480A patent/EP0793269B1/fr not_active Expired - Lifetime
- 1997-02-19 DE DE69712562T patent/DE69712562T2/de not_active Expired - Fee Related
- 1997-02-28 JP JP04585797A patent/JP4117042B2/ja not_active Expired - Fee Related
- 1997-02-28 US US08/808,591 patent/US5844321A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0793269A1 (fr) | 1997-09-03 |
| DE69712562D1 (de) | 2002-06-20 |
| JP4117042B2 (ja) | 2008-07-09 |
| JPH09237857A (ja) | 1997-09-09 |
| EP0793269B1 (fr) | 2002-05-15 |
| US5844321A (en) | 1998-12-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |