JP4117042B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4117042B2
JP4117042B2 JP04585797A JP4585797A JP4117042B2 JP 4117042 B2 JP4117042 B2 JP 4117042B2 JP 04585797 A JP04585797 A JP 04585797A JP 4585797 A JP4585797 A JP 4585797A JP 4117042 B2 JP4117042 B2 JP 4117042B2
Authority
JP
Japan
Prior art keywords
layer
substrate
via opening
semiconductor device
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04585797A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09237857A5 (enExample
JPH09237857A (ja
Inventor
ボーデ ピエール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips NV, Koninklijke Philips Electronics NV filed Critical Koninklijke Philips NV
Publication of JPH09237857A publication Critical patent/JPH09237857A/ja
Publication of JPH09237857A5 publication Critical patent/JPH09237857A5/ja
Application granted granted Critical
Publication of JP4117042B2 publication Critical patent/JP4117042B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders

Landscapes

  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Die Bonding (AREA)
JP04585797A 1996-02-28 1997-02-28 半導体装置 Expired - Fee Related JP4117042B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9602492 1996-02-28
FR9602492 1996-02-28

Publications (3)

Publication Number Publication Date
JPH09237857A JPH09237857A (ja) 1997-09-09
JPH09237857A5 JPH09237857A5 (enExample) 2005-02-03
JP4117042B2 true JP4117042B2 (ja) 2008-07-09

Family

ID=9489670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04585797A Expired - Fee Related JP4117042B2 (ja) 1996-02-28 1997-02-28 半導体装置

Country Status (4)

Country Link
US (1) US5844321A (enExample)
EP (1) EP0793269B1 (enExample)
JP (1) JP4117042B2 (enExample)
DE (1) DE69712562T2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210242162A1 (en) * 2018-06-26 2021-08-05 Sumitomo Electric Device Innovations, Inc. Method of manufacturing semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3724110B2 (ja) * 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
US20080099537A1 (en) * 2006-10-31 2008-05-01 Raytheon Company Method for sealing vias in a substrate
DE102009028037A1 (de) * 2009-07-27 2011-02-03 Robert Bosch Gmbh Bauelement mit einer elektrischen Durchkontaktierung, Verfahren zur Herstellung eines Bauelementes und Bauelementsystem
US9576873B2 (en) * 2011-12-14 2017-02-21 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with routable trace and method of manufacture thereof
US10861792B2 (en) 2019-03-25 2020-12-08 Raytheon Company Patterned wafer solder diffusion barrier

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02162735A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置及びその製造方法
US5027189A (en) * 1990-01-10 1991-06-25 Hughes Aircraft Company Integrated circuit solder die-attach design and method
FR2665574B1 (fr) * 1990-08-03 1997-05-30 Thomson Composants Microondes Procede d'interconnexion entre un circuit integre et un circuit support, et circuit integre adapte a ce procede.
US5350662A (en) * 1992-03-26 1994-09-27 Hughes Aircraft Company Maskless process for forming refractory metal layer in via holes of GaAs chips
US5635762A (en) * 1993-05-18 1997-06-03 U.S. Philips Corporation Flip chip semiconductor device with dual purpose metallized ground conductor
JP3350152B2 (ja) 1993-06-24 2002-11-25 三菱電機株式会社 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210242162A1 (en) * 2018-06-26 2021-08-05 Sumitomo Electric Device Innovations, Inc. Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
EP0793269B1 (fr) 2002-05-15
DE69712562D1 (de) 2002-06-20
US5844321A (en) 1998-12-01
EP0793269A1 (fr) 1997-09-03
DE69712562T2 (de) 2002-12-19
JPH09237857A (ja) 1997-09-09

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