DE69624174T2 - FET mit stabiler Schwellwertspannung und dessen Herstellungsverfahren - Google Patents

FET mit stabiler Schwellwertspannung und dessen Herstellungsverfahren

Info

Publication number
DE69624174T2
DE69624174T2 DE69624174T DE69624174T DE69624174T2 DE 69624174 T2 DE69624174 T2 DE 69624174T2 DE 69624174 T DE69624174 T DE 69624174T DE 69624174 T DE69624174 T DE 69624174T DE 69624174 T2 DE69624174 T2 DE 69624174T2
Authority
DE
Germany
Prior art keywords
region
implantation
implantation region
concentration
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69624174T
Other languages
German (de)
English (en)
Other versions
DE69624174D1 (de
Inventor
Diann Dow
Vida Ilderem
Michael H. Kaneshiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69624174D1 publication Critical patent/DE69624174D1/de
Publication of DE69624174T2 publication Critical patent/DE69624174T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69624174T 1995-07-07 1996-07-01 FET mit stabiler Schwellwertspannung und dessen Herstellungsverfahren Expired - Fee Related DE69624174T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/499,624 US5675166A (en) 1995-07-07 1995-07-07 FET with stable threshold voltage and method of manufacturing the same

Publications (2)

Publication Number Publication Date
DE69624174D1 DE69624174D1 (de) 2002-11-14
DE69624174T2 true DE69624174T2 (de) 2003-02-13

Family

ID=23986023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624174T Expired - Fee Related DE69624174T2 (de) 1995-07-07 1996-07-01 FET mit stabiler Schwellwertspannung und dessen Herstellungsverfahren

Country Status (6)

Country Link
US (2) US5675166A (show.php)
EP (1) EP0752722B1 (show.php)
JP (1) JPH0936367A (show.php)
CN (1) CN1141509A (show.php)
DE (1) DE69624174T2 (show.php)
TW (1) TW303520B (show.php)

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JPH1050988A (ja) * 1996-07-31 1998-02-20 Sharp Corp 絶縁ゲート型電界効果トランジスタ及びその製造方法
US5834355A (en) * 1996-12-31 1998-11-10 Intel Corporation Method for implanting halo structures using removable spacer
KR100223846B1 (ko) * 1997-05-28 1999-10-15 구본준 반도체 소자 및 그의 제조방법
DE19812945A1 (de) * 1998-03-24 1999-09-30 Siemens Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6232166B1 (en) * 1998-11-06 2001-05-15 Advanced Micro Devices, Inc. CMOS processing employing zero degree halo implant for P-channel transistor
US6211023B1 (en) * 1998-11-12 2001-04-03 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor
US6198131B1 (en) * 1998-12-07 2001-03-06 United Microelectronics Corp. High-voltage metal-oxide semiconductor
FR2794898B1 (fr) 1999-06-11 2001-09-14 France Telecom Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication
FR2796204B1 (fr) * 1999-07-07 2003-08-08 St Microelectronics Sa Transistor mosfet a canal court
US6168999B1 (en) * 1999-09-07 2001-01-02 Advanced Micro Devices, Inc. Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain
US6426278B1 (en) * 1999-10-07 2002-07-30 International Business Machines Corporation Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos
US7192836B1 (en) * 1999-11-29 2007-03-20 Advanced Micro Devices, Inc. Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance
US6624035B1 (en) * 2000-03-13 2003-09-23 Advanced Micro Devices, Inc. Method of forming a hard mask for halo implants
US6433372B1 (en) 2000-03-17 2002-08-13 International Business Machines Corporation Dense multi-gated device design
US6344405B1 (en) * 2000-04-11 2002-02-05 Philips Electronics North America Corp. Transistors having optimized source-drain structures and methods for making the same
JP3831598B2 (ja) * 2000-10-19 2006-10-11 三洋電機株式会社 半導体装置とその製造方法
US6509241B2 (en) 2000-12-12 2003-01-21 International Business Machines Corporation Process for fabricating an MOS device having highly-localized halo regions
DE10148794B4 (de) * 2001-10-02 2005-11-17 Infineon Technologies Ag Verfahren zum Herstellen eines MOS-Transistors und MOS-Transistor
US20030062571A1 (en) * 2001-10-03 2003-04-03 Franca-Neto Luiz M. Low noise microwave transistor based on low carrier velocity dispersion control
US6756276B1 (en) * 2002-09-30 2004-06-29 Advanced Micro Devices, Inc. Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication
KR100953332B1 (ko) * 2002-12-31 2010-04-20 동부일렉트로닉스 주식회사 반도체 장치의 제조 방법
KR100981674B1 (ko) * 2003-04-29 2010-09-13 매그나칩 반도체 유한회사 반도체 소자 및 그의 제조방법
KR100487927B1 (ko) * 2003-07-21 2005-05-09 주식회사 하이닉스반도체 마그네틱 램의 형성방법
US7071069B2 (en) * 2003-12-22 2006-07-04 Chartered Semiconductor Manufacturing, Ltd Shallow amorphizing implant for gettering of deep secondary end of range defects
KR100574172B1 (ko) * 2003-12-23 2006-04-27 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
KR100552808B1 (ko) * 2003-12-24 2006-02-20 동부아남반도체 주식회사 확산 소스/드레인 구조를 갖는 반도체 소자 및 그 제조 방법
US7397081B2 (en) * 2004-12-13 2008-07-08 International Business Machines Corporation Sidewall semiconductor transistors
DE102005004355B4 (de) * 2005-01-31 2008-12-18 Infineon Technologies Ag Halbleitereinrichtung und Verfahren zu deren Herstellung
EP1717850A1 (en) * 2005-04-29 2006-11-02 STMicroelectronics S.r.l. Method of manufacturing a lateral power MOS transistor
US7282406B2 (en) * 2006-03-06 2007-10-16 Semiconductor Companents Industries, L.L.C. Method of forming an MOS transistor and structure therefor
SG136058A1 (en) * 2006-03-10 2007-10-29 Chartered Semiconductor Mfg Integrated circuit system with double doped drain transistor
US8354718B2 (en) * 2007-05-22 2013-01-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including an arrangement for suppressing short channel effects
US8163619B2 (en) * 2009-03-27 2012-04-24 National Semiconductor Corporation Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
KR101700572B1 (ko) * 2010-10-20 2017-02-01 삼성전자주식회사 저농도 채널 불순물 영역을 갖는 반도체 소자
KR101714613B1 (ko) * 2010-10-28 2017-03-10 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
JP2014036082A (ja) * 2012-08-08 2014-02-24 Renesas Electronics Corp 半導体装置およびその製造方法
CN104078360B (zh) * 2013-03-28 2016-11-23 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
US11488871B2 (en) * 2013-09-24 2022-11-01 Samar K. Saha Transistor structure with multiple halo implants having epitaxial layer over semiconductor-on-insulator substrate
US9847233B2 (en) 2014-07-29 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9484417B1 (en) * 2015-07-22 2016-11-01 Globalfoundries Inc. Methods of forming doped transition regions of transistor structures
CN113410139B (zh) * 2020-07-02 2025-06-03 台积电(中国)有限公司 半导体结构及其形成方法
CN113871451B (zh) * 2021-09-24 2024-06-18 华虹半导体(无锡)有限公司 Dmos器件及其形成方法

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JPS5736862A (en) * 1980-08-13 1982-02-27 Toshiba Corp Semiconductor device
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
US5894158A (en) * 1991-09-30 1999-04-13 Stmicroelectronics, Inc. Having halo regions integrated circuit device structure
US5583067A (en) * 1993-01-22 1996-12-10 Intel Corporation Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication
JPH0799315A (ja) * 1993-06-22 1995-04-11 Motorola Inc 半導体デバイスの対向するドープ領域のインターフェースにおけるキャリア濃度を制御する方法
US5371394A (en) * 1993-11-15 1994-12-06 Motorola, Inc. Double implanted laterally diffused MOS device and method thereof
US5372960A (en) * 1994-01-04 1994-12-13 Motorola, Inc. Method of fabricating an insulated gate semiconductor device
US5668024A (en) * 1996-07-17 1997-09-16 Taiwan Semiconductor Manufacturing Company CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
KR100205320B1 (ko) * 1996-10-25 1999-07-01 구본준 모스펫 및 그 제조방법

Also Published As

Publication number Publication date
US5675166A (en) 1997-10-07
EP0752722B1 (en) 2002-10-09
TW303520B (show.php) 1997-04-21
EP0752722A2 (en) 1997-01-08
JPH0936367A (ja) 1997-02-07
US6017798A (en) 2000-01-25
DE69624174D1 (de) 2002-11-14
EP0752722A3 (en) 1998-06-10
CN1141509A (zh) 1997-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee