KR100981674B1 - 반도체 소자 및 그의 제조방법 - Google Patents
반도체 소자 및 그의 제조방법 Download PDFInfo
- Publication number
- KR100981674B1 KR100981674B1 KR1020030026973A KR20030026973A KR100981674B1 KR 100981674 B1 KR100981674 B1 KR 100981674B1 KR 1020030026973 A KR1020030026973 A KR 1020030026973A KR 20030026973 A KR20030026973 A KR 20030026973A KR 100981674 B1 KR100981674 B1 KR 100981674B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- ion implantation
- substrate
- region
- sides
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000005468 ion implantation Methods 0.000 claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 125000005843 halogen group Chemical group 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 125000004429 atom Chemical group 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims 1
- 125000001475 halogen functional group Chemical group 0.000 abstract 2
- -1 halo ions Chemical class 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 150000004820 halides Chemical class 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (13)
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 삭제
- 기판상에 게이트절연막과 게이트전극을 적층 형성하는 단계;상기 게이트전극 양측의 상기 기판의 표면내에 LDD 영역을 형성하는 단계;상기 게이트전극 가장자리 하부 및 양측의 상기 기판내에 P이온을 주입하여 제 1 할로이온주입영역을 형성하는 단계;상기 게이트전극 가장자리 하부 및 양측의 상기 기판의 표면내에 Sb이온을 주입하여 상기 제 1 할로이온주입영역 상측에 위치하도록 제 2 할로이온주입영역을 형성하는 단계;1차 열처리를 실시하는 단계;상기 게이트전극의 양측면에 측벽절연막을 형성하는 단계;상기 게이트전극 및 상기 측벽절연막 양측의 상기 기판내에 소오스/드레인영역을 형성하는 단계; 및2차 열처리를 실시하는 단계를 포함하는 반도체 소자의 제조방법.
- 제 7 항에 있어서,상기 제 1 할로이온주입영역은 P이온을 이온주입 에너지는 40~60KeV, 이온주입량은 4 ~ 6e13 atoms/㎠, 이온 주입 각은 25~45 도의 조건으로, 상기 LDD영역 하부의 상기 기판내에 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서,상기 제 1 할로이온주입영역 및 상기 제 2 할로이온주입영역은 이온주입량을 4회로 나누어 상기 기판을 90 도씩 돌려가면서 4번 이온 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서,상기 제 2 할로이온주입영역은 Sb이온을 이온주입 에너지는 80~120KeV, 이온주입량은 2 ~ 4e13 atoms/㎠, 이온 주입 각은 25~45 도의 조건으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서,상기 측벽절연막을 형성하는 단계는,화로(Furnace)에서 상기 게이트전극을 포함한 상기 기판의 전면에 제 1, 제 2 절연막을 증착하는 단계와,상기 게이트전극 양측면에만 남도록 상기 제 2, 제 1 절연막을 플라즈마 식각하여 상기 게이트전극의 측면 및 이에 인접한 상기 기판상에 이중의 제 1, 제 2 측벽절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 11 항에 있어서,상기 제 1 절연막은 고온저압증착 방식의 산화막으로 형성하고, 상기 제 2 절연막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서,상기 게이트전극과 상기 소오스/드레인영역의 표면에 실리사이드층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030026973A KR100981674B1 (ko) | 2003-04-29 | 2003-04-29 | 반도체 소자 및 그의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030026973A KR100981674B1 (ko) | 2003-04-29 | 2003-04-29 | 반도체 소자 및 그의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040095942A KR20040095942A (ko) | 2004-11-16 |
KR100981674B1 true KR100981674B1 (ko) | 2010-09-13 |
Family
ID=37374752
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030026973A KR100981674B1 (ko) | 2003-04-29 | 2003-04-29 | 반도체 소자 및 그의 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100981674B1 (ko) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6017798A (en) * | 1995-07-07 | 2000-01-25 | Motorola, Inc. | FET with stable threshold voltage and method of manufacturing the same |
KR100247810B1 (ko) * | 1997-12-22 | 2000-03-15 | 김영환 | 모스 트랜지스터 제조방법 |
-
2003
- 2003-04-29 KR KR1020030026973A patent/KR100981674B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6017798A (en) * | 1995-07-07 | 2000-01-25 | Motorola, Inc. | FET with stable threshold voltage and method of manufacturing the same |
KR100247810B1 (ko) * | 1997-12-22 | 2000-03-15 | 김영환 | 모스 트랜지스터 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20040095942A (ko) | 2004-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100761354B1 (ko) | 다면채널을 갖는 반도체소자의 듀얼폴리게이트 및 그의형성 방법 | |
KR100861835B1 (ko) | 듀얼 게이트 cmos형 반도체 소자의 제조 방법 | |
JP2004303789A (ja) | 半導体装置及びその製造方法 | |
KR100874957B1 (ko) | 오프셋 스페이서를 갖는 반도체 소자의 제조방법 및 관련된소자 | |
JP5060002B2 (ja) | 半導体装置の製造方法 | |
KR100981674B1 (ko) | 반도체 소자 및 그의 제조방법 | |
KR100519507B1 (ko) | 반도체 소자의 제조방법 | |
KR100685879B1 (ko) | 반도체 소자 및 그 제조방법 | |
KR100880336B1 (ko) | 반도체 소자의 제조방법 | |
KR100853982B1 (ko) | 3차원 전계효과 트랜지스터 및 그 제조방법 | |
KR100680943B1 (ko) | 반도체 소자의 트랜지스터 형성방법 | |
KR100995330B1 (ko) | 반도체소자의 제조방법 | |
KR100604568B1 (ko) | 반도체 소자의 제조 방법 | |
KR100386623B1 (ko) | 반도체 소자의 제조방법 | |
KR100567031B1 (ko) | 반도체 소자의 제조방법 | |
KR100832711B1 (ko) | 반도체 소자의 제조방법 | |
KR100529447B1 (ko) | 반도체 장치의 모스 트랜지스터 제조 방법 | |
KR100458770B1 (ko) | 반도체 소자의 제조 방법 | |
KR100778862B1 (ko) | 반도체 소자 및 그 제조방법 | |
KR100604537B1 (ko) | 반도체 소자의 제조 방법 | |
KR100973091B1 (ko) | Mos 트랜지스터 제조 방법 | |
KR100448591B1 (ko) | 반도체 소자의 트랜지스터 제조 방법 | |
KR100357173B1 (ko) | 박막 트랜지스터의 제조 방법 | |
KR20030001750A (ko) | 반도체 소자의 제조방법 | |
KR20100059048A (ko) | Cmos 트랜지스터의 리버스 쇼트 채널 효과 개선 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E90F | Notification of reason for final refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130821 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20140820 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20150818 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20160817 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20170818 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20180820 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20190819 Year of fee payment: 10 |