DE69618505T2 - Anfertigungs- und Zusammenstellungsverfahren einer Chipkarte und nach diesem Verfahren hergestellte Karte - Google Patents

Anfertigungs- und Zusammenstellungsverfahren einer Chipkarte und nach diesem Verfahren hergestellte Karte

Info

Publication number
DE69618505T2
DE69618505T2 DE69618505T DE69618505T DE69618505T2 DE 69618505 T2 DE69618505 T2 DE 69618505T2 DE 69618505 T DE69618505 T DE 69618505T DE 69618505 T DE69618505 T DE 69618505T DE 69618505 T2 DE69618505 T2 DE 69618505T2
Authority
DE
Germany
Prior art keywords
card
manufacturing
produced according
assembly process
chip card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69618505T
Other languages
English (en)
Other versions
DE69618505D1 (de
Inventor
Francois Launay
Jacques Venambre
Jan Severin
Noort Harry Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia France SAS
Original Assignee
Oberthur Card Systems SA France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oberthur Card Systems SA France filed Critical Oberthur Card Systems SA France
Publication of DE69618505D1 publication Critical patent/DE69618505D1/de
Application granted granted Critical
Publication of DE69618505T2 publication Critical patent/DE69618505T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE69618505T 1995-07-11 1996-07-04 Anfertigungs- und Zusammenstellungsverfahren einer Chipkarte und nach diesem Verfahren hergestellte Karte Expired - Lifetime DE69618505T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9508369A FR2736740A1 (fr) 1995-07-11 1995-07-11 Procede de production et d'assemblage de carte a circuit integre et carte ainsi obtenue

Publications (2)

Publication Number Publication Date
DE69618505D1 DE69618505D1 (de) 2002-02-21
DE69618505T2 true DE69618505T2 (de) 2002-08-29

Family

ID=9480879

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69618505T Expired - Lifetime DE69618505T2 (de) 1995-07-11 1996-07-04 Anfertigungs- und Zusammenstellungsverfahren einer Chipkarte und nach diesem Verfahren hergestellte Karte

Country Status (5)

Country Link
US (1) US5850690A (de)
EP (1) EP0753827B1 (de)
JP (1) JPH0930171A (de)
DE (1) DE69618505T2 (de)
FR (1) FR2736740A1 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7158031B2 (en) * 1992-08-12 2007-01-02 Micron Technology, Inc. Thin, flexible, RFID label and system for use
JPH09327990A (ja) * 1996-06-11 1997-12-22 Toshiba Corp カード型記憶装置
FR2756648B1 (fr) * 1996-11-29 1999-01-08 Solaic Sa Carte a memoire du type sans contact
US6329213B1 (en) 1997-05-01 2001-12-11 Micron Technology, Inc. Methods for forming integrated circuits within substrates
US6088901A (en) * 1997-06-10 2000-07-18 Siemens Aktiengesellschaft Method for producing a carrier element for semiconductor chips
US6339385B1 (en) 1997-08-20 2002-01-15 Micron Technology, Inc. Electronic communication devices, methods of forming electrical communication devices, and communication methods
FR2769389B1 (fr) * 1997-10-07 2000-01-28 Rue Cartes Et Systemes De Carte a microcircuit combinant des plages de contact exterieur et une antenne, et procede de fabrication d'une telle carte
FR2769441A1 (fr) * 1997-10-07 1999-04-09 Philips Electronics Nv Carte electronique sans contact et son procede de fabrication
FR2786317B1 (fr) * 1998-11-24 2002-12-27 Gemplus Card Int Procede de fabrication de carte a puce a contact affleurant utilisant une etape de gravure au laser et carte a puce obtenue par le procede
FR2795204B1 (fr) * 1999-06-17 2001-08-31 Gemplus Card Int Procede pour la fabrication d'un support de memorisation comportant une grille de metallisation tridimensionnelle support obtenu
JP3532123B2 (ja) * 1999-07-06 2004-05-31 日本圧着端子製造株式会社 集積回路内蔵カード
FR2799678A1 (fr) * 1999-10-15 2001-04-20 Information Technology Dev Disposition d'insertion d'une etiquette electronique sans contact, dans un objet, et procedes de mise en oeuvre
FI112288B (fi) * 2000-01-17 2003-11-14 Rafsec Oy Menetelmä älytarrasyöttörainan valmistamiseksi
FI112287B (fi) * 2000-03-31 2003-11-14 Rafsec Oy Menetelmä tuoteanturin muodostamiseksi ja tuoteanturi
FI111881B (fi) * 2000-06-06 2003-09-30 Rafsec Oy Älykorttiraina ja menetelmä sen valmistamiseksi
FI112121B (fi) 2000-12-11 2003-10-31 Rafsec Oy Älytarraraina, menetelmä sen valmistamiseksi, menetelmä kantorainan valmistamiseksi ja älytarrarainan älytarran rakenneosa
FI112550B (fi) * 2001-05-31 2003-12-15 Rafsec Oy Älytarra ja älytarraraina
FI117331B (fi) * 2001-07-04 2006-09-15 Rafsec Oy Menetelmä ruiskuvaletun tuotteen valmistamiseksi
TW561802B (en) * 2001-09-26 2003-11-11 Triplex Electronic Co Ltd Printed circuit board and the manufacturing process thereof
FR2833801B1 (fr) * 2001-12-19 2005-07-01 Oberthur Card Syst Sa Procede de realisation d'une carte a microcircuit
FI119401B (fi) * 2001-12-21 2008-10-31 Upm Raflatac Oy Älytarraraina ja menetelmä sen valmistamiseksi
US7367503B2 (en) * 2002-11-13 2008-05-06 Sandisk Corporation Universal non-volatile memory card used with various different standard cards containing a memory controller
DE10340129B4 (de) * 2003-08-28 2006-07-13 Infineon Technologies Ag Elektronisches Modul mit Steckkontakten und Verfahren zur Herstellung desselben
FR2861201B1 (fr) * 2003-10-17 2006-01-27 Oberthur Card Syst Sa Procede de fabrication d'une carte a double interface, et carte a microcircuit ainsi obtenue.
US6929485B1 (en) * 2004-03-16 2005-08-16 Agilent Technologies, Inc. Lead frame with interdigitated pins
FR2895547B1 (fr) * 2005-12-26 2008-06-06 Oberthur Card Syst Sa Procede de fabrication d'une carte a microcircuit
US20080179404A1 (en) * 2006-09-26 2008-07-31 Advanced Microelectronic And Automation Technology Ltd. Methods and apparatuses to produce inlays with transponders
TWI485825B (zh) * 2009-07-28 2015-05-21 Xintec Inc 晶片封裝體及其形成方法
USD691610S1 (en) * 2011-11-07 2013-10-15 Blackberry Limited Device smart card
US8950681B2 (en) 2011-11-07 2015-02-10 Blackberry Limited Universal integrated circuit card apparatus and related methods
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD703208S1 (en) * 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
EP3276655A1 (de) * 2016-07-26 2018-01-31 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Verfahren und system zum verbinden eines chips mit einem substrat

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714709A (en) * 1970-07-06 1973-02-06 Rca Corp Method of manufacturing thick-film hybrid integrated circuits
SU657680A1 (ru) * 1977-01-31 1979-04-15 Предприятие П/Я В-2438 Способ проводного электрического монтажа микросхем
FR2439438A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Ruban porteur de dispositifs de traitement de signaux electriques, son procede de fabrication et application de ce ruban a un element de traitement de signaux
DE3116078A1 (de) * 1981-04-22 1983-01-20 IVO Irion & Vosseler, Zählerfabrik GmbH & Co, 7730 Villingen-Schwenningen "praegefolie"
FR2520541A1 (fr) * 1982-01-22 1983-07-29 Flonic Sa Procede d'insertion d'un circuit integre dans une carte a memoire et carte obtenue suivant ce procede
DE3248385A1 (de) * 1982-12-28 1984-06-28 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit integriertem schaltkreis
US4578573A (en) * 1983-03-23 1986-03-25 Datakey, Inc. Portable electronic information devices and method of manufacture
FR2548857B1 (fr) * 1983-07-04 1987-11-27 Cortaillod Cables Sa Procede de fabrication en continu d'une carte imprimee
JPS61108195A (ja) * 1984-11-01 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 基板上に電気的に連続した層を形成する方法
FR2579798B1 (fr) * 1985-04-02 1990-09-28 Ebauchesfabrik Eta Ag Procede de fabrication de modules electroniques pour cartes a microcircuits et modules obtenus selon ce procede
FR2581480A1 (fr) * 1985-04-10 1986-11-07 Ebauches Electroniques Sa Unite electronique notamment pour carte a microcircuits et carte comprenant une telle unite
FR2580416B1 (fr) * 1985-04-12 1987-06-05 Radiotechnique Compelec Procede et dispositif pour fabriquer une carte d'identification electronique
JPS6276640A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 半導体集積回路装置
US4855868A (en) * 1987-01-20 1989-08-08 Harding Ade Yemi S K Preformed packaging arrangement for energy dissipating devices
GB8706857D0 (en) * 1987-03-23 1987-04-29 Bradley International Ltd Alle Chip carriers
ATE56050T1 (de) * 1987-04-24 1990-09-15 Siemens Ag Verfahren zur herstellung von leiterplatten.
US4859632A (en) * 1987-12-28 1989-08-22 Siemens Corporate Research And Support, Inc. Method for manufacturing the same
WO1990000813A1 (en) * 1988-07-08 1990-01-25 Oki Electric Industry Co., Ltd. Semiconductor device
JPH0220032A (ja) * 1988-07-08 1990-01-23 Seikosha Co Ltd 半導体素子の樹脂封止方法
US5081520A (en) * 1989-05-16 1992-01-14 Minolta Camera Kabushiki Kaisha Chip mounting substrate having an integral molded projection and conductive pattern
FR2662000A1 (fr) * 1990-05-11 1991-11-15 Philips Composants Carte a microcircuit.
JP2875591B2 (ja) * 1990-05-29 1999-03-31 沖電気工業株式会社 半導体装置及びその製造方法
FR2674052A1 (fr) * 1991-03-15 1992-09-18 Philips Composants Carte a microcircuit.
FR2677785A1 (fr) * 1991-06-17 1992-12-18 Philips Composants Procede de fabrication d'une carte a microcircuit.
FR2684471B1 (fr) * 1991-12-02 1994-03-04 Solaic Procede de fabrication d'une carte a memoire et carte a memoire ainsi obtenue.
DE4235019C1 (de) * 1992-10-16 1994-04-21 Ame Gmbh Leiterplattenherstellung sowie Montage- und Kontaktierungsverfahren für Bauelemente durch stromlose Metallabscheidung
ES2112992T3 (es) * 1992-09-16 1998-04-16 Inst Nat Rech Inf Automat Filtro adaptable.
ES2135656T3 (es) * 1994-06-15 1999-11-01 Rue Cartes Et Systemes De Procedimiento de fabricacion y ensamblaje de una tarjeta con circuito integrado.

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Publication number Publication date
DE69618505D1 (de) 2002-02-21
EP0753827B1 (de) 2002-01-16
US5850690A (en) 1998-12-22
EP0753827A1 (de) 1997-01-15
JPH0930171A (ja) 1997-02-04
FR2736740A1 (fr) 1997-01-17

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