DE69617192D1 - Laminat und verfahren für die herstellung einer ohmschen elektrode - Google Patents

Laminat und verfahren für die herstellung einer ohmschen elektrode

Info

Publication number
DE69617192D1
DE69617192D1 DE69617192T DE69617192T DE69617192D1 DE 69617192 D1 DE69617192 D1 DE 69617192D1 DE 69617192 T DE69617192 T DE 69617192T DE 69617192 T DE69617192 T DE 69617192T DE 69617192 D1 DE69617192 D1 DE 69617192D1
Authority
DE
Germany
Prior art keywords
film
image
ohmic electrode
fabricating
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69617192T
Other languages
English (en)
Other versions
DE69617192T2 (de
Inventor
Mitsuhiro-Sony Corpor Nakamura
Masura-Sony Corporation Wada
Chihiro-Dept Of Metal Uchibori
Masanori-Dep Of Metal Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69617192D1 publication Critical patent/DE69617192D1/de
Application granted granted Critical
Publication of DE69617192T2 publication Critical patent/DE69617192T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Laminated Bodies (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Light Receiving Elements (AREA)
  • Bipolar Transistors (AREA)
DE69617192T 1995-08-24 1996-08-20 Laminat und verfahren für die herstellung einer ohmschen elektrode Expired - Fee Related DE69617192T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP23912095 1995-08-24
PCT/JP1996/002318 WO1997008744A1 (fr) 1995-08-24 1996-08-20 Lamine permettant de former une electrode ohmique et electrode ohmique

Publications (2)

Publication Number Publication Date
DE69617192D1 true DE69617192D1 (de) 2002-01-03
DE69617192T2 DE69617192T2 (de) 2002-07-18

Family

ID=17040094

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69617192T Expired - Fee Related DE69617192T2 (de) 1995-08-24 1996-08-20 Laminat und verfahren für die herstellung einer ohmschen elektrode

Country Status (14)

Country Link
US (1) US20040238891A1 (de)
EP (1) EP0789387B1 (de)
JP (1) JP4048284B2 (de)
KR (1) KR970707572A (de)
CN (1) CN1107339C (de)
AT (1) ATE209394T1 (de)
AU (1) AU6709996A (de)
BR (1) BR9606606A (de)
CA (1) CA2203557A1 (de)
DE (1) DE69617192T2 (de)
ES (1) ES2165515T3 (de)
MY (1) MY118640A (de)
TW (1) TW307926B (de)
WO (1) WO1997008744A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040214417A1 (en) * 2003-03-11 2004-10-28 Paul Rich Methods of forming tungsten or tungsten containing films
US20050175770A1 (en) * 2004-02-10 2005-08-11 Eastman Kodak Company Fabricating an electrode for use in organic electronic devices
CN100479102C (zh) * 2006-08-29 2009-04-15 中国科学院声学研究所 一种图形化铂/钛金属薄膜的剥离制备方法
JP5621228B2 (ja) * 2009-08-27 2014-11-12 富士通株式会社 半導体装置及びその製造方法
JP5437114B2 (ja) * 2010-03-02 2014-03-12 次世代パワーデバイス技術研究組合 半導体トランジスタの製造方法
JP2011204717A (ja) * 2010-03-24 2011-10-13 Sanken Electric Co Ltd 化合物半導体装置
JP5674106B2 (ja) * 2010-09-30 2015-02-25 国立大学法人 東京大学 半導体デバイス、その製造方法及び集積回路
CN102306626B (zh) * 2011-09-09 2013-06-12 电子科技大学 半导体异质结场效应晶体管栅结构的制备方法
US20150152543A1 (en) * 2013-10-30 2015-06-04 Skyworks Solutions, Inc. Systems, devices and methods related to reactive evaporation of refractory materials
EP2881982B1 (de) 2013-12-05 2019-09-04 IMEC vzw Verfahren zur Herstellung CMOS-kompatibler Kontaktschichten in Halbleitervorrichtungen
US10096550B2 (en) 2017-02-21 2018-10-09 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures
US10224285B2 (en) 2017-02-21 2019-03-05 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166556A (ja) * 1987-12-23 1989-06-30 Hitachi Ltd n型GaAsオーム性電極およびその形成方法
US4833042A (en) * 1988-01-27 1989-05-23 Rockwell International Corporation Nonalloyed ohmic contacts for n type gallium arsenide
SE465211B (sv) * 1990-01-10 1991-08-12 Bahco Verktyg Ab Batteridrivet handverktyg
US5027187A (en) * 1990-03-22 1991-06-25 Harris Corporation Polycrystalline silicon ohmic contacts to group III-arsenide compound semiconductors
US5089438A (en) * 1991-04-26 1992-02-18 At&T Bell Laboratories Method of making an article comprising a TiNx layer
JP3180501B2 (ja) * 1993-03-12 2001-06-25 ソニー株式会社 オーミック電極の形成方法
JP3584481B2 (ja) * 1993-09-21 2004-11-04 ソニー株式会社 オーミック電極の形成方法およびオーミック電極形成用積層体
JPH1166556A (ja) * 1997-08-14 1999-03-09 Hightech Syst:Kk 磁気カード用テープ及び穴開け機

Also Published As

Publication number Publication date
CA2203557A1 (en) 1997-03-06
CN1165583A (zh) 1997-11-19
EP0789387B1 (de) 2001-11-21
EP0789387A4 (de) 1997-09-03
MX9702916A (es) 1997-09-30
EP0789387A1 (de) 1997-08-13
JP4048284B2 (ja) 2008-02-20
TW307926B (de) 1997-06-11
BR9606606A (pt) 1997-09-16
ATE209394T1 (de) 2001-12-15
US20040238891A1 (en) 2004-12-02
MY118640A (en) 2004-12-31
KR970707572A (ko) 1997-12-01
CN1107339C (zh) 2003-04-30
DE69617192T2 (de) 2002-07-18
AU6709996A (en) 1997-03-19
ES2165515T3 (es) 2002-03-16
WO1997008744A1 (fr) 1997-03-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee