DE69616981D1 - Verfahren zur ätzung eines polysiliziummusters - Google Patents

Verfahren zur ätzung eines polysiliziummusters

Info

Publication number
DE69616981D1
DE69616981D1 DE69616981T DE69616981T DE69616981D1 DE 69616981 D1 DE69616981 D1 DE 69616981D1 DE 69616981 T DE69616981 T DE 69616981T DE 69616981 T DE69616981 T DE 69616981T DE 69616981 D1 DE69616981 D1 DE 69616981D1
Authority
DE
Germany
Prior art keywords
polysilizium
etching
pattern
polysilizium pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69616981T
Other languages
English (en)
Other versions
DE69616981T2 (de
Inventor
Scott Bell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69616981D1 publication Critical patent/DE69616981D1/de
Application granted granted Critical
Publication of DE69616981T2 publication Critical patent/DE69616981T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69616981T 1995-11-08 1996-09-06 Verfahren zur ätzung eines polysiliziummusters Expired - Lifetime DE69616981T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/554,412 US5767018A (en) 1995-11-08 1995-11-08 Method of etching a polysilicon pattern
PCT/US1996/014323 WO1997017725A2 (en) 1995-11-08 1996-09-06 Method of etching a polysilicon pattern

Publications (2)

Publication Number Publication Date
DE69616981D1 true DE69616981D1 (de) 2001-12-20
DE69616981T2 DE69616981T2 (de) 2002-06-27

Family

ID=24213230

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69616981T Expired - Lifetime DE69616981T2 (de) 1995-11-08 1996-09-06 Verfahren zur ätzung eines polysiliziummusters

Country Status (5)

Country Link
US (1) US5767018A (de)
EP (1) EP0804804B1 (de)
DE (1) DE69616981T2 (de)
TW (1) TW432531B (de)
WO (1) WO1997017725A2 (de)

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US6291356B1 (en) 1997-12-08 2001-09-18 Applied Materials, Inc. Method for etching silicon oxynitride and dielectric antireflection coatings
US6066567A (en) * 1997-12-18 2000-05-23 Advanced Micro Devices, Inc. Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
JP3252780B2 (ja) * 1998-01-16 2002-02-04 日本電気株式会社 シリコン層のエッチング方法
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US6294459B1 (en) * 1998-09-03 2001-09-25 Micron Technology, Inc. Anti-reflective coatings and methods for forming and using same
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US6187687B1 (en) 1998-11-05 2001-02-13 Advanced Micro Devices, Inc. Minimization of line width variation in photolithography
US6074905A (en) * 1998-12-28 2000-06-13 Taiwan Semiconductor Manufacturing Company Formation of a thin oxide protection layer at poly sidewall and area surface
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US6228760B1 (en) 1999-03-08 2001-05-08 Taiwan Semiconductor Manufacturing Company Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish
US6299788B1 (en) * 1999-03-29 2001-10-09 Mosel Vitelic Inc. Silicon etching process
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US6174818B1 (en) * 1999-11-19 2001-01-16 Taiwan Semiconductor Manufacturing Company Method of patterning narrow gate electrode
US6605543B1 (en) * 1999-12-30 2003-08-12 Koninklijke Philips Electronics N.V. Process to control etch profiles in dual-implanted silicon films
US6300251B1 (en) * 2000-02-10 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon
US6774043B2 (en) * 2000-04-12 2004-08-10 Renesas Technology Corp. Method of manufacturing semiconductor device
US6509228B1 (en) * 2000-08-29 2003-01-21 United Microelectronics Corp. Etching procedure for floating gate formation of a flash memory device
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TW501181B (en) 2001-04-04 2002-09-01 Chartered Semiconductor Mfg Removal of organic anti-reflection coatings in integrated circuits
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US7473377B2 (en) 2002-06-27 2009-01-06 Tokyo Electron Limited Plasma processing method
US20040018739A1 (en) * 2002-07-26 2004-01-29 Applied Materials, Inc. Methods for etching using building blocks
KR100476931B1 (ko) * 2002-09-19 2005-03-16 삼성전자주식회사 시즈닝 레서피의 최적화 방법
US6900002B1 (en) * 2002-11-19 2005-05-31 Advanced Micro Devices, Inc. Antireflective bi-layer hardmask including a densified amorphous carbon layer
JP2005317684A (ja) * 2004-04-27 2005-11-10 Eudyna Devices Inc ドライエッチング方法および半導体装置
DE102004034223B3 (de) * 2004-07-15 2006-04-27 Infineon Technologies Ag Verfahren zum Trockenätzen
US20060032833A1 (en) * 2004-08-10 2006-02-16 Applied Materials, Inc. Encapsulation of post-etch halogenic residue
KR100856325B1 (ko) * 2005-12-29 2008-09-03 동부일렉트로닉스 주식회사 반도체 소자의 절연막 및 그 형성 방법
US7851369B2 (en) * 2006-06-05 2010-12-14 Lam Research Corporation Hardmask trim method
US8187483B2 (en) 2006-08-11 2012-05-29 Jason Plumhoff Method to minimize CD etch bias
JP5057107B2 (ja) * 2006-10-12 2012-10-24 日産化学工業株式会社 ４層系積層体による半導体装置の製造方法
JP5180121B2 (ja) * 2009-02-20 2013-04-10 東京エレクトロン株式会社 基板処理方法
JP5250476B2 (ja) * 2009-05-11 2013-07-31 株式会社日立ハイテクノロジーズ ドライエッチング方法
US9378971B1 (en) 2014-12-04 2016-06-28 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US10297459B2 (en) 2013-09-20 2019-05-21 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US9543158B2 (en) 2014-12-04 2017-01-10 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US9887097B2 (en) 2014-12-04 2018-02-06 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US9384998B2 (en) 2014-12-04 2016-07-05 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US10170324B2 (en) 2014-12-04 2019-01-01 Lam Research Corporation Technique to tune sidewall passivation deposition conformality for high aspect ratio cylinder etch
US9620377B2 (en) 2014-12-04 2017-04-11 Lab Research Corporation Technique to deposit metal-containing sidewall passivation for high aspect ratio cylinder etch
US9997373B2 (en) 2014-12-04 2018-06-12 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
US9543148B1 (en) 2015-09-01 2017-01-10 Lam Research Corporation Mask shrink layer for high aspect ratio dielectric etch
US10497578B2 (en) * 2016-07-22 2019-12-03 Applied Materials, Inc. Methods for high temperature etching a material layer using protection coating
US9941142B1 (en) * 2017-01-12 2018-04-10 International Business Machines Corporation Tunable TiOxNy hardmask for multilayer patterning
US10504912B2 (en) 2017-07-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology
US10276398B2 (en) 2017-08-02 2019-04-30 Lam Research Corporation High aspect ratio selective lateral etch using cyclic passivation and etching
US10276378B1 (en) * 2017-10-30 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming funnel-like opening for semiconductor device structure
US10847374B2 (en) 2017-10-31 2020-11-24 Lam Research Corporation Method for etching features in a stack
US10658174B2 (en) 2017-11-21 2020-05-19 Lam Research Corporation Atomic layer deposition and etch for reducing roughness
WO2019113482A1 (en) * 2017-12-08 2019-06-13 Tokyo Electron Limited High aspect ratio via etch using atomic layer deposition protection layer
US10361092B1 (en) 2018-02-23 2019-07-23 Lam Research Corporation Etching features using metal passivation
JP7434272B2 (ja) 2018-07-27 2024-02-20 アプライド マテリアルズ インコーポレイテッド ３ｄｎａｎｄエッチング

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Also Published As

Publication number Publication date
US5767018A (en) 1998-06-16
TW432531B (en) 2001-05-01
WO1997017725A2 (en) 1997-05-15
EP0804804A2 (de) 1997-11-05
WO1997017725A3 (en) 1997-08-14
DE69616981T2 (de) 2002-06-27
EP0804804B1 (de) 2001-11-14

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8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY