DE69526789D1 - Speicheranordnung mit verbessertem Ergebnis und verbesserter Zuverlässigkeit - Google Patents

Speicheranordnung mit verbessertem Ergebnis und verbesserter Zuverlässigkeit

Info

Publication number
DE69526789D1
DE69526789D1 DE69526789T DE69526789T DE69526789D1 DE 69526789 D1 DE69526789 D1 DE 69526789D1 DE 69526789 T DE69526789 T DE 69526789T DE 69526789 T DE69526789 T DE 69526789T DE 69526789 D1 DE69526789 D1 DE 69526789D1
Authority
DE
Germany
Prior art keywords
error
improved
decoder
error identification
memory arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69526789T
Other languages
English (en)
Other versions
DE69526789T2 (de
Inventor
Maurizio Branchetti
Carla Golla
Giovanni Campardo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69526789D1 publication Critical patent/DE69526789D1/de
Application granted granted Critical
Publication of DE69526789T2 publication Critical patent/DE69526789T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69526789T 1995-09-29 1995-09-29 Speicheranordnung mit verbessertem Ergebnis und verbesserter Zuverlässigkeit Expired - Fee Related DE69526789T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830408A EP0766174B1 (de) 1995-09-29 1995-09-29 Speicheranordnung mit verbessertem Ergebnis und verbesserter Zuverlässigkeit

Publications (2)

Publication Number Publication Date
DE69526789D1 true DE69526789D1 (de) 2002-06-27
DE69526789T2 DE69526789T2 (de) 2002-11-21

Family

ID=8222023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526789T Expired - Fee Related DE69526789T2 (de) 1995-09-29 1995-09-29 Speicheranordnung mit verbessertem Ergebnis und verbesserter Zuverlässigkeit

Country Status (3)

Country Link
US (1) US5778012A (de)
EP (1) EP0766174B1 (de)
DE (1) DE69526789T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4056488B2 (ja) * 2004-03-30 2008-03-05 エルピーダメモリ株式会社 半導体装置の試験方法及び製造方法
KR100564631B1 (ko) * 2004-09-09 2006-03-29 삼성전자주식회사 커맨드 신호의 에러 검출 기능을 가지는 메모리 모듈
US20070061669A1 (en) * 2005-08-30 2007-03-15 Major Karl L Method, device and system for detecting error correction defects
JP5052070B2 (ja) 2006-08-23 2012-10-17 ルネサスエレクトロニクス株式会社 データ読み出し回路及びデータ読み出し方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058851A (en) * 1976-10-18 1977-11-15 Sperry Rand Corporation Conditional bypass of error correction for dual memory access time selection
IT1089225B (it) * 1977-12-23 1985-06-18 Honeywell Inf Systems Memoria con dispositivo rivelatore e correttore a intervento selettivo
US4604750A (en) * 1983-11-07 1986-08-05 Digital Equipment Corporation Pipeline error correction
US4612640A (en) * 1984-02-21 1986-09-16 Seeq Technology, Inc. Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
JPS6273500A (ja) * 1985-09-26 1987-04-04 Mitsubishi Electric Corp 半導体記憶装置
JP2606862B2 (ja) * 1987-12-28 1997-05-07 株式会社東芝 単−エラー検出・訂正方式
JP2583547B2 (ja) * 1988-01-13 1997-02-19 株式会社日立製作所 半導体メモリ
JP2664236B2 (ja) * 1989-02-01 1997-10-15 富士通株式会社 半導体記憶装置
US5228046A (en) * 1989-03-10 1993-07-13 International Business Machines Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature
US5117428A (en) * 1989-11-22 1992-05-26 Unisys Corporation System for memory data integrity
JPH04162300A (ja) * 1990-10-26 1992-06-05 Nec Corp 半導体メモリ
JPH04248198A (ja) * 1991-01-24 1992-09-03 Mitsubishi Electric Corp 携帯形半導体記憶装置
JPH06325595A (ja) * 1991-03-27 1994-11-25 Nec Kyushu Ltd 誤り訂正回路付きｐｒｏｍ装置
JP2821278B2 (ja) * 1991-04-15 1998-11-05 日本電気アイシーマイコンシステム株式会社 半導体集積回路
KR950003013B1 (ko) * 1992-03-30 1995-03-29 삼성전자 주식회사 틀림정정회로를 가지는 이이피롬
JP3999822B2 (ja) * 1993-12-28 2007-10-31 株式会社東芝 記憶システム

Also Published As

Publication number Publication date
EP0766174A1 (de) 1997-04-02
US5778012A (en) 1998-07-07
DE69526789T2 (de) 2002-11-21
EP0766174B1 (de) 2002-05-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee