DE69523740T2 - Digitale bicmos verzögerungskette für niedrige spannung geeignet zur verwendung über einen weiten speisespannungsbereich - Google Patents

Digitale bicmos verzögerungskette für niedrige spannung geeignet zur verwendung über einen weiten speisespannungsbereich

Info

Publication number
DE69523740T2
DE69523740T2 DE69523740T DE69523740T DE69523740T2 DE 69523740 T2 DE69523740 T2 DE 69523740T2 DE 69523740 T DE69523740 T DE 69523740T DE 69523740 T DE69523740 T DE 69523740T DE 69523740 T2 DE69523740 T2 DE 69523740T2
Authority
DE
Germany
Prior art keywords
circuit
output
input
gate
nfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69523740T
Other languages
German (de)
English (en)
Other versions
DE69523740D1 (de
Inventor
C. Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69523740D1 publication Critical patent/DE69523740D1/de
Publication of DE69523740T2 publication Critical patent/DE69523740T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
DE69523740T 1994-12-14 1995-11-16 Digitale bicmos verzögerungskette für niedrige spannung geeignet zur verwendung über einen weiten speisespannungsbereich Expired - Lifetime DE69523740T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/355,568 US5563543A (en) 1994-12-14 1994-12-14 Low-voltage BiCMOS digital delay chain suitable for operation over a wide power supply range
PCT/IB1995/001014 WO1996019868A1 (en) 1994-12-14 1995-11-16 LOW-VOLTAGE BiCMOS DIGITAL DELAY CHAIN SUITABLE FOR OPERATION OVER A WIDE POWER SUPPLY RANGE

Publications (2)

Publication Number Publication Date
DE69523740D1 DE69523740D1 (de) 2001-12-13
DE69523740T2 true DE69523740T2 (de) 2002-08-01

Family

ID=23397922

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69523740T Expired - Lifetime DE69523740T2 (de) 1994-12-14 1995-11-16 Digitale bicmos verzögerungskette für niedrige spannung geeignet zur verwendung über einen weiten speisespannungsbereich

Country Status (6)

Country Link
US (1) US5563543A (ja)
EP (1) EP0745286B1 (ja)
JP (1) JP3778566B2 (ja)
KR (1) KR100350820B1 (ja)
DE (1) DE69523740T2 (ja)
WO (1) WO1996019868A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734809B1 (en) * 1999-04-02 2004-05-11 Think Outside, Inc. Foldable keyboard
US8436670B2 (en) 2011-01-13 2013-05-07 Micron Technology, Inc. Power supply induced signal jitter compensation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2593894B2 (ja) * 1987-11-16 1997-03-26 富士通株式会社 半導体記憶装置
US4933574A (en) * 1989-01-30 1990-06-12 Integrated Device Technology, Inc. BiCMOS output driver
US4934745A (en) * 1989-08-14 1990-06-19 Senninger Irrigation, Inc. Flexible hose coupling
JPH03121618A (ja) * 1989-10-04 1991-05-23 Toshiba Corp 出力回路
US5079447A (en) * 1990-03-20 1992-01-07 Integrated Device Technology BiCMOS gates with improved driver stages
US5068548A (en) * 1990-05-15 1991-11-26 Siarc Bicmos logic circuit for basic applications
KR930006228B1 (ko) * 1990-07-20 1993-07-09 삼성전자 주식회사 신호지연회로
US5243237A (en) * 1992-01-22 1993-09-07 Samsung Semiconductor, Inc. Noninverting bi-cmos gates with propagation delays of a single bi-cmos inverter
US5430398A (en) * 1994-01-03 1995-07-04 Texas Instruments Incorporated BiCMOS buffer circuit

Also Published As

Publication number Publication date
WO1996019868A1 (en) 1996-06-27
EP0745286B1 (en) 2001-11-07
JP3778566B2 (ja) 2006-05-24
KR100350820B1 (ko) 2002-12-28
US5563543A (en) 1996-10-08
DE69523740D1 (de) 2001-12-13
KR970701450A (ko) 1997-03-17
EP0745286A1 (en) 1996-12-04
JPH09511892A (ja) 1997-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL