DE69523193D1 - PLL-Schaltung mit verringter Einrastzeit - Google Patents

PLL-Schaltung mit verringter Einrastzeit

Info

Publication number
DE69523193D1
DE69523193D1 DE69523193T DE69523193T DE69523193D1 DE 69523193 D1 DE69523193 D1 DE 69523193D1 DE 69523193 T DE69523193 T DE 69523193T DE 69523193 T DE69523193 T DE 69523193T DE 69523193 D1 DE69523193 D1 DE 69523193D1
Authority
DE
Germany
Prior art keywords
pll circuit
locking time
reduced locking
reduced
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69523193T
Other languages
English (en)
Inventor
Toyoo Kondou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69523193D1 publication Critical patent/DE69523193D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
DE69523193T 1994-02-28 1995-02-27 PLL-Schaltung mit verringter Einrastzeit Expired - Lifetime DE69523193D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3067994 1994-02-28

Publications (1)

Publication Number Publication Date
DE69523193D1 true DE69523193D1 (de) 2001-11-22

Family

ID=12310393

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69523193T Expired - Lifetime DE69523193D1 (de) 1994-02-28 1995-02-27 PLL-Schaltung mit verringter Einrastzeit

Country Status (4)

Country Link
US (1) US5534823A (de)
EP (1) EP0669722B1 (de)
KR (1) KR100204842B1 (de)
DE (1) DE69523193D1 (de)

Families Citing this family (27)

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Publication number Priority date Publication date Assignee Title
US5799246A (en) * 1994-06-21 1998-08-25 Motorola, Inc. Radio with synthesizer and VCO
JPH08316805A (ja) * 1995-05-16 1996-11-29 Nec Corp 周波数差検出回路
US5731723A (en) * 1995-12-11 1998-03-24 Texas Instruments, Incorporated Half symbol delay calibration for phase window centering
GB2312578B (en) * 1996-04-25 2000-07-05 Plessey Semiconductors Ltd Phase-locked loops
US5675292A (en) * 1996-06-05 1997-10-07 Mccune, Jr.; Earl W. Phase lock loop enabling smooth loop bandwidth switching over a wide range
EP0842583B1 (de) * 1996-06-06 2002-05-02 Koninklijke Philips Electronics N.V. Wiedergewinnung der horizontalen synchronisation
JPH1051304A (ja) * 1996-08-02 1998-02-20 Oki Electric Ind Co Ltd Ｐｌｌ
EP0836282B1 (de) * 1996-10-08 2002-06-12 Sony Corporation Empfangsvorrichtung und -verfahren und Phasenregelkreis
US6100767A (en) * 1997-09-29 2000-08-08 Sanyo Electric Co., Ltd. Phase-locked loop with improved trade-off between lock-up time and power dissipation
US5959478A (en) * 1997-10-31 1999-09-28 Vlsi Technology, Inc. Phase-locked loop having improved locking times and a method of operation therefore
US6054903A (en) * 1997-11-13 2000-04-25 Lsi Logic Corporation Dual-loop PLL with adaptive time constant reduction on first loop
EP0917292A3 (de) * 1997-11-13 2001-08-16 Lsi Logic Corporation Phasenregelschleife mit Doppelkreis
JP3851064B2 (ja) 1999-06-30 2006-11-29 インフィネオン テクノロジース アクチエンゲゼルシャフト Ｐｌｌシンセサイザ
US6462594B1 (en) * 2000-11-08 2002-10-08 Xilinx, Inc. Digitally programmable phase-lock loop for high-speed data communications
JP2003087116A (ja) 2001-09-14 2003-03-20 Nec Saitama Ltd Ｐｌｌシンセサイザ
GB2393863B (en) * 2001-09-14 2004-09-15 Nec Corp PLL synthesizer in a cellular phone
GB2383697A (en) * 2001-12-27 2003-07-02 Zarlink Semiconductor Inc Method of speeding lock of PLL
JP4364621B2 (ja) * 2003-12-04 2009-11-18 富士通マイクロエレクトロニクス株式会社 クロックジェネレータ
JP4279180B2 (ja) * 2004-03-09 2009-06-17 Ｏｋｉセミコンダクタ株式会社 局所発振回路
US7369002B2 (en) * 2005-07-28 2008-05-06 Zarlink Semiconductor, Inc. Phase locked loop fast lock method
KR100660638B1 (ko) * 2005-10-26 2006-12-21 삼성전자주식회사 고전압 발생 회로 및 이를 구비하는 반도체 장치
US7612618B2 (en) * 2006-12-04 2009-11-03 Electronics And Telecommunications Research Institute PLL apparatus for OFDM system having variable channel bands and operating method thereof
JP4641325B2 (ja) * 2007-03-16 2011-03-02 富士通株式会社 Ｐｌｌ周波数シンセサイザ
US8370318B2 (en) * 2008-12-19 2013-02-05 Oracle International Corporation Time limited lock ownership
WO2010113377A1 (ja) 2009-04-01 2010-10-07 パナソニック株式会社 デジタル周波数／位相ロックドループ
FR3071331B1 (fr) 2017-09-19 2020-02-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Boucle a verrouillage de frequence avec transistion tension/frequence rapide
CN116584714B (zh) * 2023-07-18 2023-10-20 杭州拓尔微电子有限公司 启动控制装置、电子雾化器及其模组

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4516083A (en) * 1982-05-14 1985-05-07 Motorola, Inc. Fast lock PLL having out of lock detector control of loop filter and divider
JPH0617377B2 (ja) * 1983-06-27 1994-03-09 三井石油化学工業株式会社 硬化性組成物の硬化方法
JPS6292521A (ja) * 1985-10-17 1987-04-28 Matsushita Electric Ind Co Ltd ２モ−ドｐｌｌ回路
JPH0294710A (ja) * 1988-09-29 1990-04-05 Nec Corp 周波数シンセサイザー発振器
US4926141A (en) * 1989-05-01 1990-05-15 Motorola, Inc. Frequency synthesizer with improved automatic control of loop bandwidth selection
DE3939709A1 (de) * 1989-12-01 1991-06-06 Bosch Gmbh Robert Verfahren zur abstimmung eines funksende- und/oder -empfangsgeraetes
JPH03191642A (ja) * 1989-12-20 1991-08-21 Sharp Corp Ｐｌｌ型変調回路
EP0458269B1 (de) * 1990-05-21 1995-03-08 Nec Corporation Phasenregelschleifenschaltung
JP2798142B2 (ja) * 1990-06-15 1998-09-17 三菱電機株式会社 周波数シンセサイザ
US5146187A (en) * 1991-07-01 1992-09-08 Ericsson Ge Mobile Communications Inc. Synthesizer loop filter for scanning receivers
US5389899A (en) * 1991-08-30 1995-02-14 Fujitsu Limited Frequency synthesizer having quick frequency pull in and phase lock-in
JP2945545B2 (ja) * 1992-04-02 1999-09-06 三菱電機株式会社 Ｐｌｌ回路装置および位相差検出回路装置
GB9213624D0 (en) * 1992-06-26 1992-08-12 Motorola Israel Ltd A phase lock loop
US5384550A (en) * 1992-09-18 1995-01-24 Rockwell International Corporation Loop transient response estimator for improved acquisition performance
US5420545A (en) * 1993-03-10 1995-05-30 National Semiconductor Corporation Phase lock loop with selectable frequency switching time

Also Published As

Publication number Publication date
KR100204842B1 (ko) 1999-06-15
EP0669722A2 (de) 1995-08-30
US5534823A (en) 1996-07-09
EP0669722B1 (de) 2001-10-17
KR950026124A (ko) 1995-09-18
EP0669722A3 (de) 1996-07-31

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Legal Events

Date Code Title Description
8332 No legal effect for de