DE69522976T2 - Verfahren zur Herstellung eines Substrats für die Fabrikation von Halbleitervorrichtungen aus Silizium - Google Patents

Verfahren zur Herstellung eines Substrats für die Fabrikation von Halbleitervorrichtungen aus Silizium

Info

Publication number
DE69522976T2
DE69522976T2 DE69522976T DE69522976T DE69522976T2 DE 69522976 T2 DE69522976 T2 DE 69522976T2 DE 69522976 T DE69522976 T DE 69522976T DE 69522976 T DE69522976 T DE 69522976T DE 69522976 T2 DE69522976 T2 DE 69522976T2
Authority
DE
Germany
Prior art keywords
production
silicon
substrate
semiconductor devices
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69522976T
Other languages
English (en)
Other versions
DE69522976D1 (de
Inventor
Tatsuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69522976D1 publication Critical patent/DE69522976D1/de
Application granted granted Critical
Publication of DE69522976T2 publication Critical patent/DE69522976T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/915—Separating from substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69522976T 1994-03-04 1995-03-02 Verfahren zur Herstellung eines Substrats für die Fabrikation von Halbleitervorrichtungen aus Silizium Expired - Fee Related DE69522976T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6103453A JP2820024B2 (ja) 1994-03-04 1994-03-04 シリコン半導体素子製造用基板の製造方法

Publications (2)

Publication Number Publication Date
DE69522976D1 DE69522976D1 (de) 2001-11-08
DE69522976T2 true DE69522976T2 (de) 2002-08-08

Family

ID=14354450

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69522976T Expired - Fee Related DE69522976T2 (de) 1994-03-04 1995-03-02 Verfahren zur Herstellung eines Substrats für die Fabrikation von Halbleitervorrichtungen aus Silizium

Country Status (4)

Country Link
US (1) US5653803A (de)
EP (1) EP0670589B1 (de)
JP (1) JP2820024B2 (de)
DE (1) DE69522976T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583024B1 (en) * 2001-12-06 2003-06-24 Seh America, Inc. High resistivity silicon wafer with thick epitaxial layer and method of producing same
JP2004158526A (ja) * 2002-11-05 2004-06-03 Toshiba Ceramics Co Ltd ディスクリート素子用基板およびその製造方法
US20040134418A1 (en) * 2002-11-08 2004-07-15 Taisuke Hirooka SiC substrate and method of manufacturing the same
EP2021279A2 (de) * 2006-04-13 2009-02-11 Cabot Corporation Verfahren zur herstellung von silicium durch ein verfahren mit geschlossenem kreislauf
EP2218098B1 (de) 2007-11-02 2018-08-15 President and Fellows of Harvard College Herstellung von freistehenden festkörperschichten durch thermische verarbeitung von substraten mit einem polymer
KR101580924B1 (ko) 2009-08-25 2015-12-30 삼성전자주식회사 웨이퍼 분할 장치 및 웨이퍼 분할 방법
WO2011100647A2 (en) * 2010-02-12 2011-08-18 Solexel, Inc. Double-sided reusable template for fabrication of semiconductor substrates for photovoltaic cell and microelectronics device manufacturing
CN102412356B (zh) * 2010-09-23 2015-05-13 展晶科技(深圳)有限公司 外延基板
US9502522B1 (en) * 2016-02-29 2016-11-22 Chongqing Pingwei Enterprise Co., Ltd. Mass production process of high voltage and high current Schottky diode with diffused design
DE102017128243B4 (de) * 2017-11-29 2021-09-23 Infineon Technologies Ag Bipolartransistor mit isoliertem gate, aufweisend erste und zweite feldstoppzonenbereiche, und herstellungsverfahren
KR102200437B1 (ko) * 2018-09-12 2021-01-08 주식회사 이피지 관통형 전극 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362682A (en) * 1980-04-10 1994-11-08 Massachusetts Institute Of Technology Method of producing sheets of crystalline material and devices made therefrom
US4582559A (en) * 1984-04-27 1986-04-15 Gould Inc. Method of making thin free standing single crystal films
JPS62104062A (ja) * 1985-10-30 1987-05-14 Nec Corp 半導体基板の製造方法
JPH06105702B2 (ja) * 1987-10-28 1994-12-21 株式会社東芝 半導体基板の製造方法
JPH0210727A (ja) * 1988-06-28 1990-01-16 Naoetsu Denshi Kogyo Kk 半導体ウエハの分割方法および装置
JPH05251294A (ja) * 1992-03-06 1993-09-28 Iwao Matsunaga ガリウム化合物半導体単結晶ウエハ及びその製造方法
JPH06267848A (ja) * 1993-03-10 1994-09-22 Shin Etsu Handotai Co Ltd エピタキシャルウエーハ及びその製造方法

Also Published As

Publication number Publication date
JP2820024B2 (ja) 1998-11-05
DE69522976D1 (de) 2001-11-08
JPH07245279A (ja) 1995-09-19
EP0670589B1 (de) 2001-10-04
EP0670589A1 (de) 1995-09-06
US5653803A (en) 1997-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee