DE69029913D1 - Verfahren zur Behandlung eines Substrats für Halbleiter-Bauelemente - Google Patents

Verfahren zur Behandlung eines Substrats für Halbleiter-Bauelemente

Info

Publication number
DE69029913D1
DE69029913D1 DE69029913T DE69029913T DE69029913D1 DE 69029913 D1 DE69029913 D1 DE 69029913D1 DE 69029913 T DE69029913 T DE 69029913T DE 69029913 T DE69029913 T DE 69029913T DE 69029913 D1 DE69029913 D1 DE 69029913D1
Authority
DE
Germany
Prior art keywords
treating
substrate
semiconductor components
semiconductor
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029913T
Other languages
English (en)
Other versions
DE69029913T2 (de
Inventor
Hirokazu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Naoetsu Electronics Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Naoetsu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd, Naoetsu Electronics Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of DE69029913D1 publication Critical patent/DE69029913D1/de
Application granted granted Critical
Publication of DE69029913T2 publication Critical patent/DE69029913T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
DE69029913T 1989-04-28 1990-04-26 Verfahren zur Behandlung eines Substrats für Halbleiter-Bauelemente Expired - Fee Related DE69029913T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1111372A JPH0624200B2 (ja) 1989-04-28 1989-04-28 半導体デバイス用基板の加工方法

Publications (2)

Publication Number Publication Date
DE69029913D1 true DE69029913D1 (de) 1997-03-27
DE69029913T2 DE69029913T2 (de) 1997-08-14

Family

ID=14559523

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029913T Expired - Fee Related DE69029913T2 (de) 1989-04-28 1990-04-26 Verfahren zur Behandlung eines Substrats für Halbleiter-Bauelemente

Country Status (4)

Country Link
US (1) US5045505A (de)
EP (1) EP0396326B1 (de)
JP (1) JPH0624200B2 (de)
DE (1) DE69029913T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3211604B2 (ja) * 1995-02-03 2001-09-25 株式会社日立製作所 半導体装置
EP0863553B1 (de) * 1996-09-24 2003-02-19 Mitsubishi Denki Kabushiki Kaisha Halbleiteranordnung und verfahren zur herstellung
US6232229B1 (en) 1999-11-19 2001-05-15 Micron Technology, Inc. Microelectronic device fabricating method, integrated circuit, and intermediate construction
GB2359415A (en) * 2000-02-21 2001-08-22 Westcode Semiconductors Ltd Profiling of semiconductor wafer to prevent edge breakdown
JP3683179B2 (ja) * 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
US7258931B2 (en) * 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
JP3580311B1 (ja) * 2003-03-28 2004-10-20 住友電気工業株式会社 表裏識別した矩形窒化物半導体基板
TWI314758B (en) * 2006-04-20 2009-09-11 Touch Micro System Tech Wafer having an asymmetric edge profile and method of making the same
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
CN101226904B (zh) * 2008-01-24 2010-10-27 上海申和热磁电子有限公司 具有不对称边缘轮廓的硅片及其制造方法
JP2009277947A (ja) * 2008-05-15 2009-11-26 Sumco Corp 半導体ウェーハ
JP2010092975A (ja) * 2008-10-06 2010-04-22 Hitachi Cable Ltd 窒化物半導体基板
DE102009037281B4 (de) * 2009-08-12 2013-05-08 Siltronic Ag Verfahren zur Herstellung einer polierten Halbleiterscheibe
DE102011087487A1 (de) * 2011-11-30 2013-06-06 Infineon Technologies Bipolar Gmbh & Co. Kg Halbleiterbauelement mit optimiertem Randabschluss
CN102789978B (zh) * 2012-07-26 2015-06-10 黄山市七七七电子有限公司 普通电力整流二极管芯片的生产工艺
TWI668739B (zh) * 2018-04-03 2019-08-11 環球晶圓股份有限公司 磊晶基板及其製造方法
EP3567139B1 (de) 2018-05-11 2021-04-07 SiCrystal GmbH Abgeschrägtes siliciumcarbidsubstrat und verfahren zum abschrägen
EP3567138B1 (de) 2018-05-11 2020-03-25 SiCrystal GmbH Abgeschrägtes siliciumcarbidsubstrat und verfahren zum abschrägen
CN109141324A (zh) * 2018-08-30 2019-01-04 杭州中芯晶圆半导体股份有限公司 一种精确测量硅片上下面去除量的方法
JP6939752B2 (ja) * 2018-11-19 2021-09-22 株式会社Sumco シリコンウェーハのヘリカル面取り加工方法
JP7549322B2 (ja) * 2020-04-01 2024-09-11 株式会社ノベルクリスタルテクノロジー 半導体基板及びその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL193073A (de) * 1954-03-05
GB1145392A (en) * 1967-03-08 1969-03-12 Ass Elect Ind Improvements in semi-conductor rectifiers
US3742593A (en) * 1970-12-11 1973-07-03 Gen Electric Semiconductor device with positively beveled junctions and process for its manufacture
DE2323613A1 (de) * 1973-05-10 1974-11-28 Siemens Ag Halbleiterbauelement
DE2358937C3 (de) * 1973-11-27 1976-07-15 Licentia Gmbh Thyristor fuer hochspannung im kilovoltbereich
JPS6058579B2 (ja) * 1977-07-25 1985-12-20 日本電気株式会社 半導体ウエ−ハの製造方法
JPS55113332A (en) * 1979-02-23 1980-09-01 Hitachi Ltd Manufacture of wafer
JPS58168129U (ja) * 1982-05-04 1983-11-09 株式会社東芝 半導体ウエハの面取り装置
JPH0624199B2 (ja) * 1982-07-30 1994-03-30 株式会社日立製作所 ウエハの加工方法
JPS6088535U (ja) * 1983-11-24 1985-06-18 住友電気工業株式会社 半導体ウエハ

Also Published As

Publication number Publication date
EP0396326A1 (de) 1990-11-07
US5045505A (en) 1991-09-03
JPH02291126A (ja) 1990-11-30
JPH0624200B2 (ja) 1994-03-30
DE69029913T2 (de) 1997-08-14
EP0396326B1 (de) 1997-02-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee