DE68920365D1 - Verfahren zur Polierung eines Halbleiter-Plättchens. - Google Patents

Verfahren zur Polierung eines Halbleiter-Plättchens.

Info

Publication number
DE68920365D1
DE68920365D1 DE68920365T DE68920365T DE68920365D1 DE 68920365 D1 DE68920365 D1 DE 68920365D1 DE 68920365 T DE68920365 T DE 68920365T DE 68920365 T DE68920365 T DE 68920365T DE 68920365 D1 DE68920365 D1 DE 68920365D1
Authority
DE
Germany
Prior art keywords
polishing
semiconductor wafer
wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68920365T
Other languages
English (en)
Other versions
DE68920365T2 (de
Inventor
Yuichi Saito
Shinsuke Sakai
Hisao Hayashi
Takeshi Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Sony Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63160310A external-priority patent/JP2758406B2/ja
Priority claimed from JP63180010A external-priority patent/JPH0228925A/ja
Application filed by Mitsubishi Materials Silicon Corp, Sony Corp filed Critical Mitsubishi Materials Silicon Corp
Publication of DE68920365D1 publication Critical patent/DE68920365D1/de
Application granted granted Critical
Publication of DE68920365T2 publication Critical patent/DE68920365T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/831—Of specified ceramic or electrically insulating compositions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/84—Manufacture, treatment, or detection of nanostructure
    • Y10S977/888—Shaping or removal of materials, e.g. etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE68920365T 1988-06-28 1989-06-16 Verfahren zur Polierung eines Halbleiter-Plättchens. Expired - Lifetime DE68920365T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63160310A JP2758406B2 (ja) 1988-06-28 1988-06-28 ウェーハの製造方法
JP63180010A JPH0228925A (ja) 1988-07-19 1988-07-19 ウェーハの製造方法

Publications (2)

Publication Number Publication Date
DE68920365D1 true DE68920365D1 (de) 1995-02-16
DE68920365T2 DE68920365T2 (de) 1995-06-08

Family

ID=26486854

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68920365T Expired - Lifetime DE68920365T2 (de) 1988-06-28 1989-06-16 Verfahren zur Polierung eines Halbleiter-Plättchens.

Country Status (4)

Country Link
US (1) US5096854A (de)
EP (1) EP0348757B1 (de)
KR (1) KR0145300B1 (de)
DE (1) DE68920365T2 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH046875A (ja) * 1990-04-24 1992-01-10 Mitsubishi Materials Corp シリコンウェーハ
US5157877A (en) * 1990-04-27 1992-10-27 Shin-Etsu Handotai Co., Ltd. Method for preparing a semiconductor wafer
JPH0710493Y2 (ja) * 1991-02-05 1995-03-08 株式会社エンヤシステム ウエーハ貼付板
US5169491A (en) * 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques
JP3141486B2 (ja) * 1992-01-27 2001-03-05 ソニー株式会社 半導体装置
JP3187109B2 (ja) * 1992-01-31 2001-07-11 キヤノン株式会社 半導体部材およびその製造方法
US5366924A (en) * 1992-03-16 1994-11-22 At&T Bell Laboratories Method of manufacturing an integrated circuit including planarizing a wafer
US5445996A (en) * 1992-05-26 1995-08-29 Kabushiki Kaisha Toshiba Method for planarizing a semiconductor device having a amorphous layer
MY114512A (en) * 1992-08-19 2002-11-30 Rodel Inc Polymeric substrate with polymeric microelements
JPH0669515A (ja) * 1992-08-19 1994-03-11 Fujitsu Ltd 半導体記憶装置
JP2839801B2 (ja) * 1992-09-18 1998-12-16 三菱マテリアル株式会社 ウェーハの製造方法
US5264395A (en) * 1992-12-16 1993-11-23 International Business Machines Corporation Thin SOI layer for fully depleted field effect transistors
DE69329376T2 (de) * 1992-12-30 2001-01-04 Samsung Electronics Co., Ltd. Verfahren zur Herstellung einer SOI-Transistor-DRAM
US5318927A (en) * 1993-04-29 1994-06-07 Micron Semiconductor, Inc. Methods of chemical-mechanical polishing insulating inorganic metal oxide materials
TW367551B (en) * 1993-06-17 1999-08-21 Freescale Semiconductor Inc Polishing pad and a process for polishing
US5659192A (en) * 1993-06-30 1997-08-19 Honeywell Inc. SOI substrate fabrication
BE1007281A3 (nl) * 1993-07-12 1995-05-09 Philips Electronics Nv Werkwijze voor het polijsten van een oppervlak van koper of een in hoofdzaak koper bevattende legering, magneetkop vervaardigbaar met gebruikmaking van de werkwijze, röntgenstralingcollimerend element en röntgenstralingreflecterend element, beide voorzien van een volgens de werkwijze gepolijst oppervlak en polijstmiddel geschikt voor toepassing in de werkwijze.
US5733175A (en) 1994-04-25 1998-03-31 Leach; Michael A. Polishing a workpiece using equal velocity at all points overlapping a polisher
US5562530A (en) * 1994-08-02 1996-10-08 Sematech, Inc. Pulsed-force chemical mechanical polishing
US5783497A (en) * 1994-08-02 1998-07-21 Sematech, Inc. Forced-flow wafer polisher
US5607341A (en) 1994-08-08 1997-03-04 Leach; Michael A. Method and structure for polishing a wafer during manufacture of integrated circuits
JPH08276356A (ja) * 1995-04-10 1996-10-22 Honda Motor Co Ltd セラミックスの加工方法及び加工装置
US6110820A (en) * 1995-06-07 2000-08-29 Micron Technology, Inc. Low scratch density chemical mechanical planarization process
WO1997033716A1 (en) * 1996-03-13 1997-09-18 Trustees Of The Stevens Institute Of Technology Tribochemical polishing of ceramics and metals
US5890951A (en) * 1996-04-15 1999-04-06 Lsi Logic Corporation Utility wafer for chemical-mechanical planarization
US5769691A (en) * 1996-06-14 1998-06-23 Speedfam Corp Methods and apparatus for the chemical mechanical planarization of electronic devices
US6514875B1 (en) 1997-04-28 2003-02-04 The Regents Of The University Of California Chemical method for producing smooth surfaces on silicon wafers
US6224465B1 (en) * 1997-06-26 2001-05-01 Stuart L. Meyer Methods and apparatus for chemical mechanical planarization using a microreplicated surface
US6390890B1 (en) 1999-02-06 2002-05-21 Charles J Molnar Finishing semiconductor wafers with a fixed abrasive finishing element
EP1147546A1 (de) * 1998-11-18 2001-10-24 Rodel Holdings, Inc. Verfahren zur verminderung der muldenbildungsrate während cmp in metall-halbleiter-strukturen
US6641463B1 (en) 1999-02-06 2003-11-04 Beaver Creek Concepts Inc Finishing components and elements
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
US6435952B1 (en) * 2000-06-30 2002-08-20 Lam Research Corporation Apparatus and method for qualifying a chemical mechanical planarization process
US8512580B2 (en) * 2001-09-21 2013-08-20 Lg Display Co., Ltd. Method of fabricating thin liquid crystal display device
TWI228768B (en) * 2002-08-08 2005-03-01 Jsr Corp Processing method of polishing pad for semiconductor wafer and polishing pad for semiconductor wafer
DE10243104A1 (de) * 2002-09-17 2004-03-25 Gebr. Brasseler Gmbh & Co. Kg Rotierendes Instrument aus Keramik
US7422634B2 (en) * 2005-04-07 2008-09-09 Cree, Inc. Three inch silicon carbide wafer with low warp, bow, and TTV
KR100746622B1 (ko) * 2006-06-29 2007-08-08 주식회사 하이닉스반도체 모스 트랜지스터 제조방법
JP5215773B2 (ja) * 2008-08-18 2013-06-19 株式会社ディスコ 加工方法
CN109273586A (zh) * 2018-08-17 2019-01-25 福建晶安光电有限公司 一种压电晶片及其制作方法
CN112548845B (zh) * 2021-02-19 2021-09-14 清华大学 一种基板加工方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3342652A (en) * 1964-04-02 1967-09-19 Ibm Chemical polishing of a semi-conductor substrate
FR2063961A1 (en) * 1969-10-13 1971-07-16 Radiotechnique Compelec Mechanico-chemical grinder for semi-con-ducting panels
US3740900A (en) * 1970-07-01 1973-06-26 Signetics Corp Vacuum chuck assembly for semiconductor manufacture
US3841031A (en) * 1970-10-21 1974-10-15 Monsanto Co Process for polishing thin elements
DE2247067C3 (de) * 1972-09-26 1979-08-09 Wacker-Chemitronic Gesellschaft Fuer Elektronik-Grundstoffe Mbh, 8263 Burghausen Verwendung einer Poliersuspension zum schleierfreien Polieren von Halbleiteroberflächen
JPS5218956B2 (de) * 1973-02-20 1977-05-25
US4598053A (en) * 1974-05-23 1986-07-01 Sumitomo Electric Industries, Ltd. Ceramic compacts
US4057939A (en) * 1975-12-05 1977-11-15 International Business Machines Corporation Silicon wafer polishing
JPS58114849A (ja) * 1981-12-28 1983-07-08 Fujitsu Ltd 研磨装置
JPS5944185B2 (ja) * 1982-03-04 1984-10-27 不二越機械工業株式会社 ポリシング用セラミツク定盤の固定装置
DE3517665A1 (de) * 1985-05-15 1986-11-20 Wacker-Chemitronic Gesellschaft für Elektronik-Grundstoffe mbH, 8263 Burghausen Verfahren zum polieren von siliciumscheiben

Also Published As

Publication number Publication date
EP0348757A2 (de) 1990-01-03
US5096854A (en) 1992-03-17
EP0348757B1 (de) 1995-01-04
KR900000994A (ko) 1990-01-31
DE68920365T2 (de) 1995-06-08
KR0145300B1 (ko) 1998-08-17
EP0348757A3 (en) 1990-03-07

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Legal Events

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8364 No opposition during term of opposition