DE69411229D1 - Schaltung zur Verzögerungsanpassung - Google Patents

Schaltung zur Verzögerungsanpassung

Info

Publication number
DE69411229D1
DE69411229D1 DE69411229T DE69411229T DE69411229D1 DE 69411229 D1 DE69411229 D1 DE 69411229D1 DE 69411229 T DE69411229 T DE 69411229T DE 69411229 T DE69411229 T DE 69411229T DE 69411229 D1 DE69411229 D1 DE 69411229D1
Authority
DE
Germany
Prior art keywords
adjustment circuit
delay adjustment
delay
circuit
adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69411229T
Other languages
English (en)
Other versions
DE69411229T2 (de
Inventor
Iii C Christopher Hanke
Tzu-Hui P Hu
William F Johnstone
Barry Heim
Michael W Hodel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69411229D1 publication Critical patent/DE69411229D1/de
Application granted granted Critical
Publication of DE69411229T2 publication Critical patent/DE69411229T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00117—Avoiding variations of delay due to line termination

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
  • Manipulation Of Pulses (AREA)
DE69411229T 1993-04-05 1994-03-17 Schaltung zur Verzögerungsanpassung Expired - Fee Related DE69411229T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/043,112 US5376848A (en) 1993-04-05 1993-04-05 Delay matching circuit

Publications (2)

Publication Number Publication Date
DE69411229D1 true DE69411229D1 (de) 1998-07-30
DE69411229T2 DE69411229T2 (de) 1998-12-10

Family

ID=21925558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69411229T Expired - Fee Related DE69411229T2 (de) 1993-04-05 1994-03-17 Schaltung zur Verzögerungsanpassung

Country Status (7)

Country Link
US (1) US5376848A (de)
EP (1) EP0624950B1 (de)
JP (1) JPH0738396A (de)
KR (1) KR940025164A (de)
CN (1) CN1095871A (de)
DE (1) DE69411229T2 (de)
TW (1) TW276375B (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3487309B2 (ja) * 1993-06-30 2004-01-19 株式会社ルネサステクノロジ 半導体集積回路装置
DE69413478T2 (de) * 1993-07-30 1999-02-11 Sgs Thomson Microelectronics Inverter mit Verzögerungselement mit variabler Impedanz
JP2755183B2 (ja) * 1994-09-26 1998-05-20 日本電気株式会社 低消費電力動作用のクロックジェネレータ／コントローラ内蔵ｌｓｉ
US6100734A (en) * 1994-11-30 2000-08-08 Unisys Corporation IC chip using a phase-locked loop for providing signals having different timing edges
US5532636A (en) * 1995-03-10 1996-07-02 Intel Corporation Source-switched charge pump circuit
US5684421A (en) * 1995-10-13 1997-11-04 Credence Systems Corporation Compensated delay locked loop timing vernier
US6154056A (en) * 1997-06-09 2000-11-28 Micron Technology, Inc. Tri-stating address input circuit
US6081915A (en) * 1998-03-30 2000-06-27 Motorola, Inc. Method and apparatus for reducing the time required to test an integrated circuit using slew rate control
US6127858A (en) * 1998-04-30 2000-10-03 Intel Corporation Method and apparatus for varying a clock frequency on a phase by phase basis
TW406219B (en) * 1998-08-26 2000-09-21 Via Tech Inc PLL clock generation circuit that is capable of programming frequency and skew
JP2000332598A (ja) 1999-05-17 2000-11-30 Mitsubishi Electric Corp ランダムロジック回路
FR2802733B1 (fr) * 1999-12-21 2002-02-08 St Microelectronics Sa Bascule de type d maitre-esclave securisee
JP2001237680A (ja) * 2000-02-23 2001-08-31 Fujitsu Ltd 遅延時間調整回路と遅延時間調整方法
JP2001256785A (ja) * 2000-03-13 2001-09-21 Toshiba Corp クロックバッファ回路およびこのクロックバッファ回路を有するインタフェースならびに同期型半導体記憶装置
US6748027B1 (en) * 2000-08-10 2004-06-08 Intel Corporation CMI signal timing recovery
US7091742B2 (en) * 2002-12-19 2006-08-15 Tellabs Operations, Inc. Fast ring-out digital storage circuit
US6911856B2 (en) * 2003-07-31 2005-06-28 Qualcomm Inc. Delay matching for clock distribution in a logic circuit
US7466141B2 (en) * 2004-01-30 2008-12-16 Advantest Corporation Phase measurement device, method, program, and recording medium
US7940100B2 (en) * 2007-09-24 2011-05-10 Qualcomm, Incorporated Delay circuits matching delays of synchronous circuits
US7977983B1 (en) * 2008-05-01 2011-07-12 Freescale Semiconductor, Inc. Device having synchronizing capabilities
US8536919B1 (en) 2010-10-21 2013-09-17 Altera Corporation Integrated circuits with delay matching circuitry
TWI511442B (zh) * 2012-12-24 2015-12-01 Novatek Microelectronics Corp 資料控制電路
US9467143B1 (en) * 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
KR20180031472A (ko) 2016-09-20 2018-03-28 주식회사 넥시아 디바이스 지연 제어 시스템

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8329511D0 (en) * 1983-11-04 1983-12-07 Inmos Ltd Timing apparatus
US4663546A (en) * 1986-02-20 1987-05-05 Motorola, Inc. Two state synchronizer
US4687959A (en) * 1986-03-27 1987-08-18 Motorola, Inc. Method and apparatus for access to a PLA
JPH0691431B2 (ja) * 1987-03-02 1994-11-14 沖電気工業株式会社 フリツプフロツプ回路用クロツク制御回路
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
ATE65352T1 (de) * 1987-09-17 1991-08-15 Siemens Ag Synchronisier-flipflop-schaltungsanordnung.
US4839541A (en) * 1988-06-20 1989-06-13 Unisys Corporation Synchronizer having dual feedback loops for avoiding intermediate voltage errors
JPH02237215A (ja) * 1988-10-18 1990-09-19 Mitsubishi Electric Corp 半導体集積回路
JP3225528B2 (ja) * 1991-03-26 2001-11-05 日本電気株式会社 レジスタ回路

Also Published As

Publication number Publication date
EP0624950B1 (de) 1998-06-24
KR940025164A (ko) 1994-11-19
US5376848A (en) 1994-12-27
CN1095871A (zh) 1994-11-30
TW276375B (de) 1996-05-21
JPH0738396A (ja) 1995-02-07
DE69411229T2 (de) 1998-12-10
EP0624950A3 (de) 1995-03-08
EP0624950A2 (de) 1994-11-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee