DE69322433D1 - Dynamischer Speicher mit wahlfreiem Zugriff mit Mittelspannungsgenerator zur Energieversorgungsunterbrechung beim Prüfbetrieb - Google Patents

Dynamischer Speicher mit wahlfreiem Zugriff mit Mittelspannungsgenerator zur Energieversorgungsunterbrechung beim Prüfbetrieb

Info

Publication number
DE69322433D1
DE69322433D1 DE69322433T DE69322433T DE69322433D1 DE 69322433 D1 DE69322433 D1 DE 69322433D1 DE 69322433 T DE69322433 T DE 69322433T DE 69322433 T DE69322433 T DE 69322433T DE 69322433 D1 DE69322433 D1 DE 69322433D1
Authority
DE
Germany
Prior art keywords
voltage generator
random access
test operation
intermediate voltage
interrupting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69322433T
Other languages
English (en)
Other versions
DE69322433T2 (de
Inventor
Yasuhiro Nanba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69322433D1 publication Critical patent/DE69322433D1/de
Application granted granted Critical
Publication of DE69322433T2 publication Critical patent/DE69322433T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
DE69322433T 1992-04-28 1993-04-27 Dynamischer Speicher mit wahlfreiem Zugriff mit Mittelspannungsgenerator zur Energieversorgungsunterbrechung beim Prüfbetrieb Expired - Lifetime DE69322433T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4109409A JPH0612896A (ja) 1992-04-28 1992-04-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69322433D1 true DE69322433D1 (de) 1999-01-21
DE69322433T2 DE69322433T2 (de) 1999-07-08

Family

ID=14509523

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322433T Expired - Lifetime DE69322433T2 (de) 1992-04-28 1993-04-27 Dynamischer Speicher mit wahlfreiem Zugriff mit Mittelspannungsgenerator zur Energieversorgungsunterbrechung beim Prüfbetrieb

Country Status (5)

Country Link
US (1) US5315554A (de)
EP (1) EP0568015B1 (de)
JP (1) JPH0612896A (de)
KR (1) KR960005900B1 (de)
DE (1) DE69322433T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6105152A (en) * 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
JP2697574B2 (ja) * 1993-09-27 1998-01-14 日本電気株式会社 半導体メモリ装置
KR960002330B1 (ko) * 1993-12-23 1996-02-16 현대전자산업주식회사 프리차지 전압 발생회로
JP3315293B2 (ja) * 1995-01-05 2002-08-19 株式会社東芝 半導体記憶装置
US5500824A (en) * 1995-01-18 1996-03-19 Micron Technology, Inc. Adjustable cell plate generator
WO1996038362A1 (en) * 1995-06-02 1996-12-05 The Procter & Gamble Company Method of winding logs with different sheet counts
US5667162A (en) * 1995-06-02 1997-09-16 The Procter & Gamble Company Turret winder mandrel cupping assembly
US5592422A (en) * 1995-06-07 1997-01-07 Sgs-Thomson Microelectronics, Inc. Reduced pin count stress test circuit for integrated memory devices and method therefor
KR0166505B1 (ko) * 1995-08-18 1999-02-01 김주용 분리된 다수의 내부 전원전압을 사용하는 디램 및 감지증폭기 어레이
US6459634B1 (en) * 2000-01-31 2002-10-01 Micron Technology, Inc. Circuits and methods for testing memory cells along a periphery of a memory array
KR100411993B1 (ko) * 2001-04-23 2003-12-24 한종상 비닐 백용 필름 권취 장치
KR100632369B1 (ko) 2005-02-15 2006-10-11 삼성전자주식회사 풀 스트레스로 테스트가 가능한 오픈 비트라인 구조의 메모리 디바이스 및 이에 대한 테스트 방법
TWI302311B (en) * 2006-06-09 2008-10-21 Innolux Display Corp Dynamic random access memory
KR101033803B1 (ko) * 2008-12-31 2011-05-13 한철근 롤 백 제조 장치
JP6746659B2 (ja) * 2018-11-09 2020-08-26 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． メモリデバイス及びその内蔵セルフテスト方法
CN115686164A (zh) * 2021-07-26 2023-02-03 瑞昱半导体股份有限公司 供电端装置、供电系统以及非暂态电脑可读取媒体

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010400B2 (ja) * 1980-10-09 1985-03-16 富士通株式会社 半導体集積回路装置
JPS6258500A (ja) * 1985-09-09 1987-03-14 Fujitsu Ltd 半導体記憶装置の試験方法
US5157629A (en) * 1985-11-22 1992-10-20 Hitachi, Ltd. Selective application of voltages for testing storage cells in semiconductor memory arrangements
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
KR0134773B1 (ko) * 1988-07-05 1998-04-20 Hitachi Ltd 반도체 기억장치
ATE117457T1 (de) * 1989-03-16 1995-02-15 Siemens Ag Integrierter halbleiterspeicher vom typ dram und verfahren zu seinem testen.
JPH0346193A (ja) * 1989-07-13 1991-02-27 Mitsubishi Electric Corp スタティック型半導体記憶装置
JP3037377B2 (ja) * 1990-08-27 2000-04-24 沖電気工業株式会社 半導体記憶装置
JP3050326B2 (ja) * 1990-11-30 2000-06-12 日本電気株式会社 半導体集積回路

Also Published As

Publication number Publication date
KR940006146A (ko) 1994-03-23
US5315554A (en) 1994-05-24
DE69322433T2 (de) 1999-07-08
JPH0612896A (ja) 1994-01-21
KR960005900B1 (ko) 1996-05-03
EP0568015A2 (de) 1993-11-03
EP0568015B1 (de) 1998-12-09
EP0568015A3 (de) 1995-02-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP