JPS6457490A - Dynamic ram - Google Patents

Dynamic ram

Info

Publication number
JPS6457490A
JPS6457490A JP62215579A JP21557987A JPS6457490A JP S6457490 A JPS6457490 A JP S6457490A JP 62215579 A JP62215579 A JP 62215579A JP 21557987 A JP21557987 A JP 21557987A JP S6457490 A JPS6457490 A JP S6457490A
Authority
JP
Japan
Prior art keywords
level
data
circuit
memory cell
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62215579A
Other languages
Japanese (ja)
Inventor
Yoshitomo Kimura
Heihachi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62215579A priority Critical patent/JPS6457490A/en
Publication of JPS6457490A publication Critical patent/JPS6457490A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dram (AREA)

Abstract

PURPOSE:To obtain a dynamic RAM for increasing a circuit margin, by disposing a voltage impressing circuit for impressing a negative voltage on a memory cell correspondingly to the data of 'L' level. CONSTITUTION:At the time of writing the data of 'H' level, a transistor 3 is not turned on, but a VCC is transferred to a bit line 14 and a positive voltage is stored in the capacitor 11 of the memory cell M. At the time of writing the data of the 'L' level, an inverter circuit 2 is turned on correspondingly to the data of the 'L' level to excite the transistor 3, impress the negative voltage outputted from a negative voltage generating circuit 1 to the capacitor 11 of the memory cell M through the bit line 14 and store a negative charge. Thereby, a potential difference between the 'H' level and the 'L' level at the time of reading can be increased to increase the circuit margin.
JP62215579A 1987-08-28 1987-08-28 Dynamic ram Pending JPS6457490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62215579A JPS6457490A (en) 1987-08-28 1987-08-28 Dynamic ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62215579A JPS6457490A (en) 1987-08-28 1987-08-28 Dynamic ram

Publications (1)

Publication Number Publication Date
JPS6457490A true JPS6457490A (en) 1989-03-03

Family

ID=16674774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62215579A Pending JPS6457490A (en) 1987-08-28 1987-08-28 Dynamic ram

Country Status (1)

Country Link
JP (1) JPS6457490A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219490A (en) * 1990-01-23 1991-09-26 Matsushita Electric Ind Co Ltd Sense amplifier circuit
US5255223A (en) * 1990-07-23 1993-10-19 Oki Electric Industry Co., Ltd. Semiconductor memory device having alternatively operated equalizing and erasing functions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489534A (en) * 1977-12-27 1979-07-16 Nec Corp Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489534A (en) * 1977-12-27 1979-07-16 Nec Corp Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219490A (en) * 1990-01-23 1991-09-26 Matsushita Electric Ind Co Ltd Sense amplifier circuit
US5255223A (en) * 1990-07-23 1993-10-19 Oki Electric Industry Co., Ltd. Semiconductor memory device having alternatively operated equalizing and erasing functions

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