DE69320582T2 - Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement - Google Patents

Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement

Info

Publication number
DE69320582T2
DE69320582T2 DE69320582T DE69320582T DE69320582T2 DE 69320582 T2 DE69320582 T2 DE 69320582T2 DE 69320582 T DE69320582 T DE 69320582T DE 69320582 T DE69320582 T DE 69320582T DE 69320582 T2 DE69320582 T2 DE 69320582T2
Authority
DE
Germany
Prior art keywords
gate electrode
layer
transistor
floating gate
memory element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69320582T
Other languages
German (de)
English (en)
Other versions
DE69320582D1 (de
Inventor
Andrew Jan Nl-5656 Aa Eindhoven Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69320582D1 publication Critical patent/DE69320582D1/de
Publication of DE69320582T2 publication Critical patent/DE69320582T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69320582T 1992-10-07 1993-10-04 Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement Expired - Lifetime DE69320582T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92203082 1992-10-07

Publications (2)

Publication Number Publication Date
DE69320582D1 DE69320582D1 (de) 1998-10-01
DE69320582T2 true DE69320582T2 (de) 1999-04-01

Family

ID=8210951

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69320582T Expired - Lifetime DE69320582T2 (de) 1992-10-07 1993-10-04 Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement

Country Status (7)

Country Link
US (1) US5395778A (enExample)
JP (1) JPH06236974A (enExample)
KR (1) KR100292159B1 (enExample)
CN (1) CN1050934C (enExample)
CA (1) CA2107602C (enExample)
DE (1) DE69320582T2 (enExample)
TW (1) TW237564B (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW322591B (enExample) * 1996-02-09 1997-12-11 Handotai Energy Kenkyusho Kk
TW347567B (en) * 1996-03-22 1998-12-11 Philips Eloctronics N V Semiconductor device and method of manufacturing a semiconductor device
US6429120B1 (en) 2000-01-18 2002-08-06 Micron Technology, Inc. Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
TW332342B (en) * 1996-11-11 1998-05-21 Mos Electronics Taiwan Inc Structure and fabrication method of split-gate flash memory
TW360951B (en) * 1997-04-01 1999-06-11 Nxp Bv Method of manufacturing a semiconductor device
US5885871A (en) * 1997-07-31 1999-03-23 Stmicrolelectronics, Inc. Method of making EEPROM cell structure
US6297111B1 (en) * 1997-08-20 2001-10-02 Advanced Micro Devices Self-aligned channel transistor and method for making same
TW420874B (en) * 1998-05-04 2001-02-01 Koninkl Philips Electronics Nv Method of manufacturing a semiconductor device
US6159795A (en) * 1998-07-02 2000-12-12 Advanced Micro Devices, Inc. Low voltage junction and high voltage junction optimization for flash memory
US6309936B1 (en) * 1998-09-30 2001-10-30 Advanced Micro Devices, Inc. Integrated formation of LDD and non-LDD semiconductor devices
EP0993036A1 (en) * 1998-10-09 2000-04-12 STMicroelectronics S.r.l. Method of manufacturing an integrated semiconductor device comprising a floating gate field-effect transistor and a logic-field effect transistor, and corresponding device
JP2002539637A (ja) 1999-03-17 2002-11-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ フローティングゲート電界効果型トランジスタの製造方法
US6074908A (en) * 1999-05-26 2000-06-13 Taiwan Semiconductor Manufacturing Company Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits
US6235587B1 (en) * 1999-10-13 2001-05-22 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region
US6552396B1 (en) * 2000-03-14 2003-04-22 International Business Machines Corporation Matched transistors and methods for forming the same
DE10101270A1 (de) * 2001-01-12 2002-07-25 Infineon Technologies Ag Verfahren zur Herstellung von eingebetteten nichtflüchtigen Halbleiterspeicherzellen
CN100390960C (zh) * 2001-12-31 2008-05-28 台湾茂矽电子股份有限公司 抹除快闪存储阵列存储单元的方法
KR100666615B1 (ko) * 2004-04-14 2007-01-09 매그나칩 반도체 유한회사 플래쉬 메모리 소자
US7919801B2 (en) * 2007-10-26 2011-04-05 Hvvi Semiconductors, Inc. RF power transistor structure and a method of forming the same
US8125044B2 (en) * 2007-10-26 2012-02-28 Hvvi Semiconductors, Inc. Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture
US8133783B2 (en) * 2007-10-26 2012-03-13 Hvvi Semiconductors, Inc. Semiconductor device having different structures formed simultaneously
US9660044B2 (en) * 2013-09-05 2017-05-23 Nxp Usa, Inc. Power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor
CN107425069B (zh) * 2017-07-10 2020-04-24 东南大学 面向物联网的有热电转换的soi基ldmos功率管
CN114582706B (zh) * 2020-11-30 2026-03-13 南通尚阳通集成电路有限公司 氧化层的形成方法
CN116322047A (zh) * 2023-02-27 2023-06-23 上海华力集成电路制造有限公司 一种兼容半浮栅器件和逻辑器件的制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
IT1213249B (it) * 1984-11-26 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US4859619A (en) * 1988-07-15 1989-08-22 Atmel Corporation EPROM fabrication process forming tub regions for high voltage devices
JPH0766946B2 (ja) * 1989-03-31 1995-07-19 株式会社東芝 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR940010394A (ko) 1994-05-26
CA2107602A1 (en) 1994-04-08
KR100292159B1 (ko) 2001-09-17
CA2107602C (en) 2004-01-20
JPH06236974A (ja) 1994-08-23
DE69320582D1 (de) 1998-10-01
TW237564B (enExample) 1995-01-01
US5395778A (en) 1995-03-07
CN1050934C (zh) 2000-03-29
CN1086045A (zh) 1994-04-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL