DE69231021T2 - Verfahren zur Kontrolle der Ätzkontur einer Schicht einer integrierten Schaltung - Google Patents

Verfahren zur Kontrolle der Ätzkontur einer Schicht einer integrierten Schaltung

Info

Publication number
DE69231021T2
DE69231021T2 DE69231021T DE69231021T DE69231021T2 DE 69231021 T2 DE69231021 T2 DE 69231021T2 DE 69231021 T DE69231021 T DE 69231021T DE 69231021 T DE69231021 T DE 69231021T DE 69231021 T2 DE69231021 T2 DE 69231021T2
Authority
DE
Germany
Prior art keywords
checking
layer
integrated circuit
etching contour
contour
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231021T
Other languages
English (en)
Other versions
DE69231021D1 (de
Inventor
Patrick Daniel Rabinzohn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MHS NANTES CEDEX
Original Assignee
MHS NANTES CEDEX
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MHS NANTES CEDEX filed Critical MHS NANTES CEDEX
Application granted granted Critical
Publication of DE69231021D1 publication Critical patent/DE69231021D1/de
Publication of DE69231021T2 publication Critical patent/DE69231021T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
DE69231021T 1991-08-05 1992-07-31 Verfahren zur Kontrolle der Ätzkontur einer Schicht einer integrierten Schaltung Expired - Fee Related DE69231021T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9109951A FR2680276B1 (fr) 1991-08-05 1991-08-05 Procede de controle du profil de gravure d'une couche d'un circuit integre.

Publications (2)

Publication Number Publication Date
DE69231021D1 DE69231021D1 (de) 2000-06-15
DE69231021T2 true DE69231021T2 (de) 2000-12-21

Family

ID=9415941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231021T Expired - Fee Related DE69231021T2 (de) 1991-08-05 1992-07-31 Verfahren zur Kontrolle der Ätzkontur einer Schicht einer integrierten Schaltung

Country Status (4)

Country Link
US (1) US5378309A (de)
EP (1) EP0528713B1 (de)
DE (1) DE69231021T2 (de)
FR (1) FR2680276B1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07147271A (ja) * 1993-11-26 1995-06-06 Nec Corp 半導体装置の製造方法
KR0178238B1 (ko) * 1995-09-30 1999-04-15 배순훈 박막 자기 헤드의 하부 자성층 패턴 형성 방법
US5780358A (en) * 1996-04-08 1998-07-14 Chartered Semiconductor Manufacturing Ltd. Method for chemical-mechanical polish (CMP) planarizing of cooper containing conductor layers
US5686743A (en) * 1996-07-10 1997-11-11 Trw Inc. Method of forming airbridged metallization for integrated circuit fabrication
KR100240879B1 (ko) * 1997-05-17 2000-01-15 윤종용 반도체 장치의 평탄화 방법
US6066569A (en) * 1997-09-30 2000-05-23 Siemens Aktiengesellschaft Dual damascene process for metal layers and organic intermetal layers
JP3093720B2 (ja) * 1998-04-08 2000-10-03 松下電子工業株式会社 パターン形成方法
AR018448A1 (es) 1998-06-04 2001-11-14 Pirelli Cavi E Sistemi Spa Metodo para fabricar una estructura de guia de ondas opticas difundida en un substrato, guia de ondas opticas difundida obtenida y dispositivooptico que la contiene
KR100760175B1 (ko) * 1999-07-22 2007-09-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2001035808A (ja) * 1999-07-22 2001-02-09 Semiconductor Energy Lab Co Ltd 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法
TWI286338B (en) * 2000-05-12 2007-09-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TW480576B (en) * 2000-05-12 2002-03-21 Semiconductor Energy Lab Semiconductor device and method for manufacturing same
US6409312B1 (en) 2001-03-27 2002-06-25 Lexmark International, Inc. Ink jet printer nozzle plate and process therefor
JP2003045874A (ja) * 2001-07-27 2003-02-14 Semiconductor Energy Lab Co Ltd 金属配線およびその作製方法、並びに金属配線基板およびその作製方法
US6790782B1 (en) 2001-12-28 2004-09-14 Advanced Micro Devices, Inc. Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
US6579809B1 (en) 2002-05-16 2003-06-17 Advanced Micro Devices, Inc. In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric
FR2914783A1 (fr) * 2007-04-03 2008-10-10 St Microelectronics Sa Procede de fabrication d'un dispositif a gradient de concentration et dispositif correspondant.
JP2012253056A (ja) * 2011-05-31 2012-12-20 Toshiba Corp 半導体装置の製造方法
WO2017052905A1 (en) * 2015-09-22 2017-03-30 Applied Materials, Inc. Apparatus and method for selective deposition

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4436584A (en) * 1983-03-21 1984-03-13 Sperry Corporation Anisotropic plasma etching of semiconductors
US4505782A (en) * 1983-03-25 1985-03-19 Lfe Corporation Plasma reactive ion etching of aluminum and aluminum alloys
CA1260754A (en) * 1983-12-26 1989-09-26 Teiji Majima Method for forming patterns and apparatus used for carrying out the same
FR2557740B1 (fr) * 1983-12-28 1986-08-14 Souriau & Cie Connecteur electrique
US4678540A (en) * 1986-06-09 1987-07-07 Tegal Corporation Plasma etch process

Also Published As

Publication number Publication date
EP0528713B1 (de) 2000-05-10
DE69231021D1 (de) 2000-06-15
FR2680276B1 (fr) 1997-04-25
EP0528713A1 (de) 1993-02-24
FR2680276A1 (fr) 1993-02-12
US5378309A (en) 1995-01-03

Similar Documents

Publication Publication Date Title
DE69231021T2 (de) Verfahren zur Kontrolle der Ätzkontur einer Schicht einer integrierten Schaltung
DE69305939T2 (de) Verfahren zur Herstellung eines keramischen Schaltungssubstrates
DE69309352T2 (de) Verfahren zur Überprüfung der Neigung eines Gehäuses eines integrierten Schaltkreises
DE69208324D1 (de) Verfahren zur Oberflächenbehandlung einer Kupferfolie für gedruckte Schaltungen
DE69232432T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69231803D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69232131T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung mit einer isolierenden Schicht für einen Kondensator
DE69326706D1 (de) Verfahren zur Herstellung einer Schicht auf einem Halbleiterkörper
DE69309358D1 (de) Verfahren zur Herstellung eines Schaltungssubstrats
DE68921550D1 (de) Verfahren und Gerät zur Bildung eines Pattern-Layouts einer integrierten Halbleiterschaltung.
DE69015879D1 (de) Verfahren zur Herstellung einer oberflächenmontierbaren Leiterplatte.
DE69033802T2 (de) Verfahren zur Herstellung eines Leitermusters einer integrierten Schaltungshalbleiteranordnung
DE69416808T2 (de) Verfahren zur Herstellung einer mehrschichtigen Halbleitervorrichtung
DE69227943D1 (de) Verfahren zum Herstellen einer Aluminiumnitrid-Mehrschicht-Schaltungsplatte
DE69033593D1 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einer Isolationszone
DE59010907D1 (de) Verfahren zur Erhöhung der Spannungsfestigkeit eines mehrschichtigen Halbleiterbauelements
DE69522484D1 (de) Verfahren zur Herstellung einer keramischen Leiterplatte
DE69033515D1 (de) Verfahren zur Herstellung einer integrierten Schaltung
DE69413195D1 (de) Verfahren zur Passivierung einer integrierten Schaltung
DE69123692D1 (de) Verfahren zur Herstellung einer keramischen Leiterplatte
DE69013851T2 (de) Verfahren zur Herstellung einer keramischen Schaltungsplatte.
DE69027508D1 (de) Verfahren zur Herstellung einer Mehrlagenverdrahtung für Halbleiter-integrierte Schaltung
DE69600363T2 (de) Verfahren zur Inbetriebnahme einer Halbleiterschaltung
DE69025899T2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung
DE69218035D1 (de) Verfahren zum Herstellen einer integrierten Schaltung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee