DE69027508D1 - Verfahren zur Herstellung einer Mehrlagenverdrahtung für Halbleiter-integrierte Schaltung - Google Patents

Verfahren zur Herstellung einer Mehrlagenverdrahtung für Halbleiter-integrierte Schaltung

Info

Publication number
DE69027508D1
DE69027508D1 DE69027508T DE69027508T DE69027508D1 DE 69027508 D1 DE69027508 D1 DE 69027508D1 DE 69027508 T DE69027508 T DE 69027508T DE 69027508 T DE69027508 T DE 69027508T DE 69027508 D1 DE69027508 D1 DE 69027508D1
Authority
DE
Germany
Prior art keywords
integrated circuits
semiconductor integrated
multilayer wiring
producing multilayer
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69027508T
Other languages
English (en)
Other versions
DE69027508T2 (de
Inventor
Yasukazu Mase
Masahiro Abe
Toshihiko Katsura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69027508D1 publication Critical patent/DE69027508D1/de
Application granted granted Critical
Publication of DE69027508T2 publication Critical patent/DE69027508T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE69027508T 1989-10-31 1990-10-31 Verfahren zur Herstellung einer Mehrlagenverdrahtung für Halbleiter-integrierte Schaltung Expired - Fee Related DE69027508T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1283942A JP2515408B2 (ja) 1989-10-31 1989-10-31 バイポ−ラ型半導体装置

Publications (2)

Publication Number Publication Date
DE69027508D1 true DE69027508D1 (de) 1996-07-25
DE69027508T2 DE69027508T2 (de) 1996-12-12

Family

ID=17672217

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69027508T Expired - Fee Related DE69027508T2 (de) 1989-10-31 1990-10-31 Verfahren zur Herstellung einer Mehrlagenverdrahtung für Halbleiter-integrierte Schaltung

Country Status (5)

Country Link
US (1) US5103287A (de)
EP (1) EP0426151B1 (de)
JP (1) JP2515408B2 (de)
KR (1) KR940002757B1 (de)
DE (1) DE69027508T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2555964B2 (ja) * 1993-12-10 1996-11-20 日本電気株式会社 アライメント精度調査パターン
US5596226A (en) * 1994-09-06 1997-01-21 International Business Machines Corporation Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module
US6255226B1 (en) * 1998-12-01 2001-07-03 Philips Semiconductor, Inc. Optimized metal etch process to enable the use of aluminum plugs
TW200603287A (en) * 2004-03-26 2006-01-16 Ulvac Inc Unit layer posttreating catalytic chemical vapor deposition apparatus and method of film formation therewith
JP2006339343A (ja) 2005-06-01 2006-12-14 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
JPH02100341A (ja) * 1988-10-06 1990-04-12 Toshiba Corp 半導体装置のパターン形成方法
JP2508831B2 (ja) * 1989-01-09 1996-06-19 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
EP0426151B1 (de) 1996-06-19
US5103287A (en) 1992-04-07
EP0426151A3 (en) 1993-08-11
KR910008835A (ko) 1991-05-31
JPH03145734A (ja) 1991-06-20
KR940002757B1 (ko) 1994-04-02
JP2515408B2 (ja) 1996-07-10
DE69027508T2 (de) 1996-12-12
EP0426151A2 (de) 1991-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee