DE68924468D1 - Verfahren und Struktur zur Herstellung einer Isolierung aus VLSI- und ULSI-Schaltungen. - Google Patents

Verfahren und Struktur zur Herstellung einer Isolierung aus VLSI- und ULSI-Schaltungen.

Info

Publication number
DE68924468D1
DE68924468D1 DE68924468T DE68924468T DE68924468D1 DE 68924468 D1 DE68924468 D1 DE 68924468D1 DE 68924468 T DE68924468 T DE 68924468T DE 68924468 T DE68924468 T DE 68924468T DE 68924468 D1 DE68924468 D1 DE 68924468D1
Authority
DE
Germany
Prior art keywords
vlsi
producing insulation
ulsi circuits
ulsi
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924468T
Other languages
English (en)
Other versions
DE68924468T2 (de
Inventor
Stanley Roberts
Carter Welling Kaanta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68924468D1 publication Critical patent/DE68924468D1/de
Publication of DE68924468T2 publication Critical patent/DE68924468T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE68924468T 1988-12-16 1989-11-08 Verfahren und Struktur zur Herstellung einer Isolierung aus VLSI- und ULSI-Schaltungen. Expired - Fee Related DE68924468T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/286,443 US4987101A (en) 1988-12-16 1988-12-16 Method for providing improved insulation in VLSI and ULSI circuits

Publications (2)

Publication Number Publication Date
DE68924468D1 true DE68924468D1 (de) 1995-11-09
DE68924468T2 DE68924468T2 (de) 1996-05-30

Family

ID=23098630

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924468T Expired - Fee Related DE68924468T2 (de) 1988-12-16 1989-11-08 Verfahren und Struktur zur Herstellung einer Isolierung aus VLSI- und ULSI-Schaltungen.

Country Status (4)

Country Link
US (2) US4987101A (de)
EP (1) EP0373360B1 (de)
JP (1) JPH0685415B2 (de)
DE (1) DE68924468T2 (de)

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US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
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Also Published As

Publication number Publication date
EP0373360A2 (de) 1990-06-20
JPH0685415B2 (ja) 1994-10-26
US5144411A (en) 1992-09-01
EP0373360A3 (de) 1991-02-27
DE68924468T2 (de) 1996-05-30
US4987101A (en) 1991-01-22
JPH02218150A (ja) 1990-08-30
EP0373360B1 (de) 1995-10-04

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