DE69230019T2 - Anordnung von Transistoren zur Fertigung einer Basiszelle für eine integrierte Masterslice-Halbleiteranordnung und integrierte Masterslice-Halbleiteranordnung - Google Patents

Anordnung von Transistoren zur Fertigung einer Basiszelle für eine integrierte Masterslice-Halbleiteranordnung und integrierte Masterslice-Halbleiteranordnung

Info

Publication number
DE69230019T2
DE69230019T2 DE69230019T DE69230019T DE69230019T2 DE 69230019 T2 DE69230019 T2 DE 69230019T2 DE 69230019 T DE69230019 T DE 69230019T DE 69230019 T DE69230019 T DE 69230019T DE 69230019 T2 DE69230019 T2 DE 69230019T2
Authority
DE
Germany
Prior art keywords
arrangement
master slice
integrated master
slice semiconductor
semiconductor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69230019T
Other languages
English (en)
Other versions
DE69230019D1 (de
Inventor
Junichi Shikatani
Tetsu Tanizawa
Mitsugu Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69230019D1 publication Critical patent/DE69230019D1/de
Application granted granted Critical
Publication of DE69230019T2 publication Critical patent/DE69230019T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69230019T 1991-07-18 1992-07-15 Anordnung von Transistoren zur Fertigung einer Basiszelle für eine integrierte Masterslice-Halbleiteranordnung und integrierte Masterslice-Halbleiteranordnung Expired - Fee Related DE69230019T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17812191 1991-07-18

Publications (2)

Publication Number Publication Date
DE69230019D1 DE69230019D1 (de) 1999-10-28
DE69230019T2 true DE69230019T2 (de) 2000-01-05

Family

ID=16043023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69230019T Expired - Fee Related DE69230019T2 (de) 1991-07-18 1992-07-15 Anordnung von Transistoren zur Fertigung einer Basiszelle für eine integrierte Masterslice-Halbleiteranordnung und integrierte Masterslice-Halbleiteranordnung

Country Status (4)

Country Link
US (1) US5436485A (de)
EP (1) EP0523967B1 (de)
KR (1) KR960016177B1 (de)
DE (1) DE69230019T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JPH07263628A (ja) * 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置
JP3352895B2 (ja) * 1996-12-25 2002-12-03 株式会社東芝 半導体集積回路、半導体集積回路の設計方法および製造方法
US5780883A (en) * 1997-02-28 1998-07-14 Translogic Technology, Inc. Gate array architecture for multiplexer based circuits
JP4301462B2 (ja) 1997-09-29 2009-07-22 川崎マイクロエレクトロニクス株式会社 電界効果トランジスタ
JP4279955B2 (ja) * 1998-12-08 2009-06-17 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置及びその製造方法
JP2002026296A (ja) * 2000-06-22 2002-01-25 Internatl Business Mach Corp <Ibm> 半導体集積回路装置
JP2004006514A (ja) * 2002-05-31 2004-01-08 Oki Electric Ind Co Ltd ゲートアレイ半導体装置の基本セル，ゲートアレイ半導体装置，および，ゲートアレイ半導体装置のレイアウト方法
US6804809B1 (en) * 2002-10-30 2004-10-12 Polarfab, Llc System and method for defining a semiconductor device layout
JP2011159755A (ja) * 2010-01-29 2011-08-18 Sanyo Electric Co Ltd 半導体装置
US9748246B2 (en) 2014-11-06 2017-08-29 Samsung Electronics Co., Ltd. Semiconductor integrated circuits having contacts spaced apart from active regions
EP3041052A1 (de) * 2015-01-05 2016-07-06 Ampleon Netherlands B.V. Halbleiterbauelement das einen vertikalen Bipolartransistor mit lateraler Driftregion enthält

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57100746A (en) * 1980-12-15 1982-06-23 Toshiba Corp Semiconductor integrated circuit device
JPS5944843A (ja) * 1982-09-07 1984-03-13 Mitsubishi Electric Corp 半導体集積回路装置
JPS59163837A (ja) * 1983-03-09 1984-09-14 Toshiba Corp 半導体集積回路
JPS6135535A (ja) * 1984-07-27 1986-02-20 Fujitsu Ltd マスタ−スライス集積回路装置
JPS61100947A (ja) * 1984-10-22 1986-05-19 Toshiba Corp 半導体集積回路装置
JPS63311740A (ja) * 1987-06-15 1988-12-20 Matsushita Electronics Corp 半導体集積回路装置
JPH0828485B2 (ja) * 1988-06-20 1996-03-21 日本電信電話株式会社 相補型ｍｉｓマスタスライスｌｓｉの基本セル
DE69034088T2 (de) * 1989-04-19 2004-02-05 Seiko Epson Corp. Halbleiteranordnung

Also Published As

Publication number Publication date
DE69230019D1 (de) 1999-10-28
EP0523967B1 (de) 1999-09-22
EP0523967A2 (de) 1993-01-20
EP0523967A3 (en) 1993-06-23
KR960016177B1 (ko) 1996-12-04
KR930003235A (ko) 1993-02-24
US5436485A (en) 1995-07-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

8339 Ceased/non-payment of the annual fee