DE69319963D1 - Kontaktlöcherstruktur für eine Halbleiter-Schaltung und Herstellungsverfahren - Google Patents

Kontaktlöcherstruktur für eine Halbleiter-Schaltung und Herstellungsverfahren

Info

Publication number
DE69319963D1
DE69319963D1 DE69319963T DE69319963T DE69319963D1 DE 69319963 D1 DE69319963 D1 DE 69319963D1 DE 69319963 T DE69319963 T DE 69319963T DE 69319963 T DE69319963 T DE 69319963T DE 69319963 D1 DE69319963 D1 DE 69319963D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor circuit
vias structure
vias
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69319963T
Other languages
English (en)
Other versions
DE69319963T2 (de
Inventor
Fusen E Chen
Girish A Dixit
Che-Chia Wei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69319963D1 publication Critical patent/DE69319963D1/de
Publication of DE69319963T2 publication Critical patent/DE69319963T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69319963T 1992-05-06 1993-05-06 Kontaktlöcherstruktur für eine Halbleiter-Schaltung und Herstellungsverfahren Expired - Fee Related DE69319963T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/879,190 US5317192A (en) 1992-05-06 1992-05-06 Semiconductor contact via structure having amorphous silicon side walls

Publications (2)

Publication Number Publication Date
DE69319963D1 true DE69319963D1 (de) 1998-09-03
DE69319963T2 DE69319963T2 (de) 1998-12-10

Family

ID=25373606

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69319963T Expired - Fee Related DE69319963T2 (de) 1992-05-06 1993-05-06 Kontaktlöcherstruktur für eine Halbleiter-Schaltung und Herstellungsverfahren

Country Status (4)

Country Link
US (2) US5317192A (de)
EP (1) EP0571108B1 (de)
JP (1) JPH0645466A (de)
DE (1) DE69319963T2 (de)

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JPH07297276A (ja) * 1992-09-22 1995-11-10 At & T Corp 半導体集積回路の形成方法
US5493152A (en) * 1993-11-09 1996-02-20 Vlsi Technology, Inc. Conductive via structure for integrated circuits and method for making same
US5488013A (en) * 1993-12-20 1996-01-30 International Business Machines Corporation Method of forming transverse diffusion barrier interconnect structure
US5756397A (en) * 1993-12-28 1998-05-26 Lg Semicon Co., Ltd. Method of fabricating a wiring in a semiconductor device
JPH07235537A (ja) * 1994-02-23 1995-09-05 Mitsubishi Electric Corp 表面が平坦化された半導体装置およびその製造方法
US5472913A (en) * 1994-08-05 1995-12-05 Texas Instruments Incorporated Method of fabricating porous dielectric material with a passivation layer for electronics applications
US5599749A (en) * 1994-10-21 1997-02-04 Yamaha Corporation Manufacture of micro electron emitter
KR0161731B1 (ko) * 1994-10-28 1999-02-01 김주용 반도체소자의 미세콘택 형성방법
KR0138295B1 (ko) * 1994-11-30 1998-06-01 김광호 도전선 형성방법
US5656543A (en) * 1995-02-03 1997-08-12 National Semiconductor Corporation Fabrication of integrated circuits with borderless vias
US5858875A (en) * 1995-02-03 1999-01-12 National Semiconductor Corporation Integrated circuits with borderless vias
US5757077A (en) * 1995-02-03 1998-05-26 National Semiconductor Corporation Integrated circuits with borderless vias
KR100338480B1 (ko) * 1995-08-19 2003-01-24 엘지.필립스 엘시디 주식회사 액정표시장치및그제조방법
GB2333393B (en) * 1995-08-19 2000-03-29 Lg Electronics Inc Wiring structure for a liquid crystal display device and a method of manufacturing the same.
US5675185A (en) * 1995-09-29 1997-10-07 International Business Machines Corporation Semiconductor structure incorporating thin film transistors with undoped cap oxide layers
US5640038A (en) * 1995-11-22 1997-06-17 Vlsi Technology, Inc. Integrated circuit structure with self-planarized layers
US5683930A (en) * 1995-12-06 1997-11-04 Micron Technology Inc. SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making
JPH09260492A (ja) * 1996-03-25 1997-10-03 Toshiba Corp 半導体装置の製造方法
US5723380A (en) * 1996-03-25 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of approach to improve metal lithography and via-plug integration
SG80582A1 (en) * 1997-03-20 2001-05-22 Chartered Semiconductor Mfg Use of an insulator spacer on the sidewalls of a via hole
US6015751A (en) * 1998-04-06 2000-01-18 Taiwan Semiconductor Manufacturing Company Self-aligned connection to underlayer metal lines through unlanded via holes
US6187672B1 (en) * 1998-09-22 2001-02-13 Conexant Systems, Inc. Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
US6444564B1 (en) 1998-11-23 2002-09-03 Advanced Micro Devices, Inc. Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
US6245629B1 (en) * 1999-03-25 2001-06-12 Infineon Technologies North America Corp. Semiconductor structures and manufacturing methods
US7454085B2 (en) * 2005-04-29 2008-11-18 Hewlett-Packard Development Company, L.P. Method and apparatus for the creation of textures and borders for digital images

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4489481A (en) * 1982-09-20 1984-12-25 Texas Instruments Incorporated Insulator and metallization method for VLSI devices with anisotropically-etched contact holes
JPS60198847A (ja) * 1984-03-23 1985-10-08 Nec Corp 半導体装置およびその製造方法
US4549914A (en) * 1984-04-09 1985-10-29 At&T Bell Laboratories Integrated circuit contact technique
US4640738A (en) * 1984-06-22 1987-02-03 International Business Machines Corporation Semiconductor contact protection
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
WO1987002828A1 (en) * 1985-11-04 1987-05-07 Motorola, Inc. Glass intermetal dielectric
JPS63237441A (ja) * 1987-03-25 1988-10-03 Mitsubishi Electric Corp 半導体装置
JPS63253647A (ja) * 1987-04-10 1988-10-20 Nec Corp 半導体装置
JPH0622235B2 (ja) * 1987-05-21 1994-03-23 日本電気株式会社 半導体装置の製造方法
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US4898841A (en) * 1988-06-16 1990-02-06 Northern Telecom Limited Method of filling contact holes for semiconductor devices and contact structures made by that method
JPH02144940A (ja) * 1988-11-28 1990-06-04 Hitachi Ltd 多層配線間の層間絶縁膜構造
JPH02165624A (ja) * 1988-12-20 1990-06-26 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface
JPH03239348A (ja) * 1990-02-16 1991-10-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5279990A (en) * 1990-03-02 1994-01-18 Motorola, Inc. Method of making a small geometry contact using sidewall spacers
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices
US5117273A (en) * 1990-11-16 1992-05-26 Sgs-Thomson Microelectronics, Inc. Contact for integrated circuits

Also Published As

Publication number Publication date
US5317192A (en) 1994-05-31
EP0571108B1 (de) 1998-07-29
JPH0645466A (ja) 1994-02-18
EP0571108A1 (de) 1993-11-24
DE69319963T2 (de) 1998-12-10
US5444019A (en) 1995-08-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee