DE69229104D1 - Stroboskopische Signale in Halbleiterspeicheranordnungen - Google Patents

Stroboskopische Signale in Halbleiterspeicheranordnungen

Info

Publication number
DE69229104D1
DE69229104D1 DE69229104T DE69229104T DE69229104D1 DE 69229104 D1 DE69229104 D1 DE 69229104D1 DE 69229104 T DE69229104 T DE 69229104T DE 69229104 T DE69229104 T DE 69229104T DE 69229104 D1 DE69229104 D1 DE 69229104D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory devices
stroboscopic
signals
stroboscopic signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69229104T
Other languages
English (en)
Other versions
DE69229104T2 (de
Inventor
Yun-Ho Choi
Ejaz Ul Haq
Dae-Je Chin
Soo-In Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE69229104D1 publication Critical patent/DE69229104D1/de
Application granted granted Critical
Publication of DE69229104T2 publication Critical patent/DE69229104T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE69229104T 1992-01-31 1992-10-30 Stroboskopische Signale in Halbleiterspeicheranordnungen Expired - Lifetime DE69229104T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920001461A KR950000504B1 (ko) 1992-01-31 1992-01-31 복수개의 로우 어드레스 스트로브 신호를 가지는 반도체 메모리 장치

Publications (2)

Publication Number Publication Date
DE69229104D1 true DE69229104D1 (de) 1999-06-10
DE69229104T2 DE69229104T2 (de) 1999-12-09

Family

ID=19328529

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229104T Expired - Lifetime DE69229104T2 (de) 1992-01-31 1992-10-30 Stroboskopische Signale in Halbleiterspeicheranordnungen

Country Status (7)

Country Link
US (1) US5343438A (de)
EP (1) EP0553547B1 (de)
JP (1) JP2607814B2 (de)
KR (1) KR950000504B1 (de)
CN (1) CN1078378C (de)
DE (1) DE69229104T2 (de)
TW (1) TW311725U (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US7187572B2 (en) 2002-06-28 2007-03-06 Rambus Inc. Early read after write operation memory device, system and method
JP2547633B2 (ja) * 1989-05-09 1996-10-23 三菱電機株式会社 半導体記憶装置
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
EP0561370B1 (de) * 1992-03-19 1999-06-02 Kabushiki Kaisha Toshiba Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
US6310821B1 (en) * 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
US6279116B1 (en) 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
US5680518A (en) * 1994-08-26 1997-10-21 Hangartner; Ricky D. Probabilistic computing methods and apparatus
JPH0869409A (ja) * 1994-08-29 1996-03-12 Nec Corp 半導体メモリのデータ読み出し方法
US5613094A (en) * 1994-10-17 1997-03-18 Smart Modular Technologies Method and apparatus for enabling an assembly of non-standard memory components to emulate a standard memory module
KR0146176B1 (ko) * 1995-05-02 1998-09-15 김주용 동기식 기억장치의 신호 전달 회로
JP3710845B2 (ja) 1995-06-21 2005-10-26 株式会社ルネサステクノロジ 半導体記憶装置
US5537353A (en) * 1995-08-31 1996-07-16 Cirrus Logic, Inc. Low pin count-wide memory devices and systems and methods using the same
US5652732A (en) * 1995-12-22 1997-07-29 Cypress Semiconductor Corp. Apparatus and method for matching a clock delay to a delay through a memory array
WO1997035316A1 (fr) 1996-03-21 1997-09-25 Hitachi, Ltd. Processeur a memoire dram integree
US6504548B2 (en) 1998-09-18 2003-01-07 Hitachi, Ltd. Data processing apparatus having DRAM incorporated therein
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
KR100232895B1 (ko) * 1996-12-31 1999-12-01 김영환 센스앰프 인에이블 신호 발생 장치
KR100326268B1 (ko) 1998-10-28 2002-05-09 박종섭 디코딩시의동작마진확보를위한디코딩장치및그방법
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
CN1870873A (zh) * 2005-05-28 2006-11-29 深圳富泰宏精密工业有限公司 铰链装置及应用该铰链装置的便携式电子装置
KR100755064B1 (ko) * 2005-12-13 2007-09-06 주식회사 하이닉스반도체 내부 어드레스 생성 회로
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
WO2009042329A2 (en) * 2007-09-27 2009-04-02 Rambus Inc. Reconfigurable memory system data strobes
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
WO2015153693A1 (en) * 2014-03-31 2015-10-08 Xockets IP, LLC Interface, interface methods, and systems for operating memory bus attached computing elements

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58141494A (ja) * 1982-02-15 1983-08-22 Toshiba Corp メモリアクセス装置
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
US4636986B1 (en) * 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip
JPS63163937A (ja) * 1986-12-26 1988-07-07 Minolta Camera Co Ltd メモリ制御装置
US4967397A (en) * 1989-05-15 1990-10-30 Unisys Corporation Dynamic RAM controller
JP3103575B2 (ja) * 1989-05-26 2000-10-30 松下電器産業株式会社 半導体記憶装置
JPH03160685A (ja) * 1989-11-17 1991-07-10 Wacom Co Ltd Ｄｒａｍアクセス方法及びその装置
US4998222A (en) * 1989-12-04 1991-03-05 Nec Electronics Inc. Dynamic random access memory with internally gated RAS

Also Published As

Publication number Publication date
US5343438A (en) 1994-08-30
KR950000504B1 (ko) 1995-01-24
TW311725U (en) 1997-07-21
EP0553547B1 (de) 1999-05-06
JPH0660640A (ja) 1994-03-04
CN1075025A (zh) 1993-08-04
KR930017028A (ko) 1993-08-30
CN1078378C (zh) 2002-01-23
DE69229104T2 (de) 1999-12-09
EP0553547A2 (de) 1993-08-04
EP0553547A3 (en) 1993-12-08
JP2607814B2 (ja) 1997-05-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition