DE69222356T2 - Mit elektrischen Leitungen versehenes Substrat und dessen Herstellungsverfahren - Google Patents

Mit elektrischen Leitungen versehenes Substrat und dessen Herstellungsverfahren

Info

Publication number
DE69222356T2
DE69222356T2 DE69222356T DE69222356T DE69222356T2 DE 69222356 T2 DE69222356 T2 DE 69222356T2 DE 69222356 T DE69222356 T DE 69222356T DE 69222356 T DE69222356 T DE 69222356T DE 69222356 T2 DE69222356 T2 DE 69222356T2
Authority
DE
Germany
Prior art keywords
manufacturing process
substrate provided
electrical leads
leads
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69222356T
Other languages
English (en)
Other versions
DE69222356D1 (de
Inventor
Masaharu Shirai
Kimihiro Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69222356D1 publication Critical patent/DE69222356D1/de
Application granted granted Critical
Publication of DE69222356T2 publication Critical patent/DE69222356T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
DE69222356T 1991-05-31 1992-05-28 Mit elektrischen Leitungen versehenes Substrat und dessen Herstellungsverfahren Expired - Fee Related DE69222356T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3156123A JPH04354398A (ja) 1991-05-31 1991-05-31 配線基板及びその製造方法

Publications (2)

Publication Number Publication Date
DE69222356D1 DE69222356D1 (de) 1997-10-30
DE69222356T2 true DE69222356T2 (de) 1998-03-26

Family

ID=15620829

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69222356T Expired - Fee Related DE69222356T2 (de) 1991-05-31 1992-05-28 Mit elektrischen Leitungen versehenes Substrat und dessen Herstellungsverfahren

Country Status (5)

Country Link
US (2) US5252781A (de)
EP (1) EP0516402B1 (de)
JP (1) JPH04354398A (de)
DE (1) DE69222356T2 (de)
HK (1) HK1011458A1 (de)

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CA2055148C (en) * 1991-10-25 2002-06-18 Alain Langevin Method of forming an electrically conductive contact on a substrate
US5471090A (en) * 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
JPH07101699B2 (ja) * 1993-09-29 1995-11-01 インターナショナル・ビジネス・マシーンズ・コーポレイション 印刷回路基板及び液晶表示装置
EP0723387A1 (de) * 1995-01-19 1996-07-24 Digital Equipment Corporation Absperrung von Oberflächenmontage-Kontaktflächen einer Leiterplatte durch eine Lötstopmaske
CN1080981C (zh) 1995-06-06 2002-03-13 揖斐电株式会社 印刷电路板
US5691509A (en) * 1995-09-11 1997-11-25 Balzano; Alfiero Flexible cable termination and connector system
US6115910A (en) * 1997-05-08 2000-09-12 Lsi Logic Corporation Misregistration fidutial
JP2000003977A (ja) 1998-06-16 2000-01-07 Shinko Electric Ind Co Ltd 半導体チップ実装用基板
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
US6341071B1 (en) 1999-03-19 2002-01-22 International Business Machines Corporation Stress relieved ball grid array package
CN1178232C (zh) * 1999-04-26 2004-12-01 松下电器产业株式会社 电子零件及无线终端装置
US6774474B1 (en) * 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
DE10164879B4 (de) * 2000-03-02 2006-06-08 Murata Manufacturing Co., Ltd., Nagaokakyo Verdrahtungssubstrat
JP2001320168A (ja) 2000-03-02 2001-11-16 Murata Mfg Co Ltd 配線基板およびその製造方法、ならびにそれを用いた電子装置
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US20060163729A1 (en) * 2001-04-18 2006-07-27 Mou-Shiung Lin Structure and manufacturing method of a chip scale package
JP3581111B2 (ja) * 2001-05-01 2004-10-27 新光電気工業株式会社 半導体素子の実装基板及び実装構造
US20040032562A1 (en) * 2001-05-01 2004-02-19 Three-Five Systems, Inc. Method and apparatus for adjusting contrast during assembly of liquid crystal displays and similar devices
US7149090B2 (en) * 2001-09-11 2006-12-12 Brother Kogyo Kabushiki Kaisha Structure of flexible printed circuit board
US6667090B2 (en) * 2001-09-26 2003-12-23 Intel Corporation Coupon registration mechanism and method
US7180005B2 (en) * 2002-05-17 2007-02-20 Nec Corporation Printed wiring board
US7531898B2 (en) 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US6960828B2 (en) 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
JP4196875B2 (ja) 2004-04-26 2008-12-17 ブラザー工業株式会社 プリント基板及びそれを用いたインクジェットヘッド
US7190157B2 (en) * 2004-10-25 2007-03-13 Agilent Technologies, Inc. Method and apparatus for layout independent test point placement on a printed circuit board
WO2006053036A2 (en) * 2004-11-10 2006-05-18 Unitive International Limited Non-circular via holes for bumping pads and related structures
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US7646567B2 (en) * 2005-06-28 2010-01-12 Seagate Technology Llc Flex on suspension with a heat-conducting protective layer for reflowing solder interconnects
JP2007227731A (ja) * 2006-02-24 2007-09-06 Matsushita Electric Ind Co Ltd プリント基板とそれを用いた電子機器
TWI340612B (en) * 2007-07-24 2011-04-11 Advanced Semiconductor Eng Circuit substrate and method for fabricating inductive circuit
US8013254B2 (en) 2008-02-15 2011-09-06 Gigalane Co. Ltd. Printed circuit board
US7952834B2 (en) * 2008-02-22 2011-05-31 Seagate Technology Llc Flex circuit assembly with thermal energy dissipation
JP2010258302A (ja) * 2009-04-27 2010-11-11 Texas Instr Japan Ltd 超音波フリップチップ実装方法およびそれに用いられる基板
US8669777B2 (en) 2010-10-27 2014-03-11 Seagate Technology Llc Assessing connection joint coverage between a device and a printed circuit board
JP6024078B2 (ja) * 2011-08-17 2016-11-09 大日本印刷株式会社 サスペンション用基板
KR102529998B1 (ko) * 2015-04-30 2023-05-08 엘지이노텍 주식회사 인쇄회로기판, 이를 포함하는 렌즈 구동장치 및 카메라 모듈
EP3088931A1 (de) * 2015-04-30 2016-11-02 LG Innotek Co., Ltd. Linsenbewegungsvorrichtung und kameramodul sowie optische vorrichtung damit
CN105979716A (zh) * 2016-05-20 2016-09-28 泉州三宝电子有限公司 一种柔性电路板及其制造方法
JP6884835B2 (ja) * 2019-09-27 2021-06-09 サンコール株式会社 バスバーアッセンブリ及びその製造方法

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JPS5680196A (en) * 1979-12-05 1981-07-01 Hitachi Ltd Method of forming electrode for printed circuit board
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JPS63302595A (ja) * 1987-06-02 1988-12-09 Murata Mfg Co Ltd チップ部品の取付構造
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EP0439546A1 (de) * 1988-10-20 1991-08-07 Siemens Aktiengesellschaft Verfahren und vorrichtung zum löten von drähten von bauelementen zur montage auf oberflächen
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Also Published As

Publication number Publication date
US5517756A (en) 1996-05-21
HK1011458A1 (en) 1999-07-09
DE69222356D1 (de) 1997-10-30
EP0516402A1 (de) 1992-12-02
US5252781A (en) 1993-10-12
JPH04354398A (ja) 1992-12-08
EP0516402B1 (de) 1997-09-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee