DE69128602T2 - Eingangspufferschaltung mit einer auf einem Übergang basierten Verriegelung - Google Patents

Eingangspufferschaltung mit einer auf einem Übergang basierten Verriegelung

Info

Publication number
DE69128602T2
DE69128602T2 DE69128602T DE69128602T DE69128602T2 DE 69128602 T2 DE69128602 T2 DE 69128602T2 DE 69128602 T DE69128602 T DE 69128602T DE 69128602 T DE69128602 T DE 69128602T DE 69128602 T2 DE69128602 T2 DE 69128602T2
Authority
DE
Germany
Prior art keywords
buffer circuit
input buffer
transition based
based latch
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128602T
Other languages
English (en)
Other versions
DE69128602D1 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69128602D1 publication Critical patent/DE69128602D1/de
Publication of DE69128602T2 publication Critical patent/DE69128602T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Manipulation Of Pulses (AREA)
  • Dram (AREA)
DE69128602T 1990-10-22 1991-10-21 Eingangspufferschaltung mit einer auf einem Übergang basierten Verriegelung Expired - Fee Related DE69128602T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/601,287 US5124584A (en) 1990-10-22 1990-10-22 Address buffer circuit with transition-based latching

Publications (2)

Publication Number Publication Date
DE69128602D1 DE69128602D1 (de) 1998-02-12
DE69128602T2 true DE69128602T2 (de) 1998-04-16

Family

ID=24406938

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128602T Expired - Fee Related DE69128602T2 (de) 1990-10-22 1991-10-21 Eingangspufferschaltung mit einer auf einem Übergang basierten Verriegelung

Country Status (5)

Country Link
US (1) US5124584A (de)
EP (1) EP0482868B1 (de)
JP (1) JP3375143B2 (de)
KR (1) KR920009082A (de)
DE (1) DE69128602T2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459693A (en) * 1990-06-14 1995-10-17 Creative Integrated Systems, Inc. Very large scale integrated planar read only memory
US5258952A (en) * 1990-12-14 1993-11-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with separate time-out control for read and write operations
JPH0562470A (ja) * 1991-08-29 1993-03-12 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US5153455A (en) * 1991-10-07 1992-10-06 Advanced Micro Devices, Inc. Transition-based wired "OR" for VLSI systems
US5306963A (en) * 1992-06-19 1994-04-26 Intel Corporation Address transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memory
US5329182A (en) * 1992-08-12 1994-07-12 Motorola Inc. ATD pulse generator circuit with ECL to CMOS level conversion
KR0136074B1 (ko) * 1992-09-11 1998-06-01 세키자와 스토무 개량된 소프트 에러 저항을 갖는 mos형 sram, 고전위 전원 전압 강하 검출 회로, 상보 신호 천이 검출 회로 및 개량된 내부신호 시간 마진을 갖는 반도체 장치
KR950004855B1 (ko) * 1992-10-30 1995-05-15 현대전자산업 주식회사 반도체 메모리 소자의 어드레스 전이 검출 회로
US5414312A (en) * 1993-07-15 1995-05-09 Altera Corporation Advanced signal driving buffer with directional input transition detection
US5438548A (en) * 1993-12-10 1995-08-01 Texas Instruments Incorporated Synchronous memory with reduced power access mode
US5418479A (en) * 1993-12-27 1995-05-23 Intel Corporation Method and circuitry for generating a safe address transition pulse in a memory device
US5491444A (en) * 1993-12-28 1996-02-13 Sgs-Thomson Microelectronics, Inc. Fuse circuit with feedback disconnect
US5579326A (en) * 1994-01-31 1996-11-26 Sgs-Thomson Microelectronics, Inc. Method and apparatus for programming signal timing
US5493537A (en) * 1994-02-28 1996-02-20 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with edge transition detection pulse disable
US5471157A (en) * 1994-03-31 1995-11-28 Sgs-Thomson Microelectronics, Inc. Integrated circuit with centralized control of edge transition detection pulse generation
US5475320A (en) * 1994-08-11 1995-12-12 Texas Instruments Incorporated Data processing with a self-timed approach to spurious transitions
EP0703530A3 (de) * 1994-09-21 1996-08-14 Texas Instruments Inc Erkennung in der Veränderung des Logikzustands in einem Datenverarbeitungssystem
US5493538A (en) * 1994-11-14 1996-02-20 Texas Instruments Incorporated Minimum pulse width address transition detection circuit
US5576636A (en) * 1995-08-15 1996-11-19 Intel Corporation Low power programmable logic arrays
US5629896A (en) * 1995-08-31 1997-05-13 Sgs-Thomson Microelectronics, Inc. Write controlled address buffer
KR0167300B1 (ko) * 1995-12-21 1999-02-01 문정환 메모리의 어드레스 천이 검출회로
KR0172420B1 (ko) * 1995-12-27 1999-03-30 김광호 고속의 어드레스 입력을 위한 어드레스 버퍼
JP3903588B2 (ja) * 1997-07-31 2007-04-11 ソニー株式会社 信号変化検出回路
US6603338B1 (en) 1998-10-30 2003-08-05 Stmicroelectronics, Inc. Device and method for address input buffering
US6294939B1 (en) * 1998-10-30 2001-09-25 Stmicroelectronics, Inc. Device and method for data input buffering
KR100522830B1 (ko) * 1998-12-30 2006-01-12 주식회사 하이닉스반도체 데이터 입력 버퍼 회로
US5978281A (en) * 1999-01-04 1999-11-02 International Business Machines Corporation Method and apparatus for preventing postamble corruption within a memory system
GB2346462B (en) * 1999-02-05 2003-11-26 Gec Marconi Comm Ltd Memories
JP2003007071A (ja) 2001-06-26 2003-01-10 Sharp Corp 半導体メモリ装置
KR100587690B1 (ko) * 2004-10-13 2006-06-08 삼성전자주식회사 어드레스 버퍼 회로 및 어드레스 버퍼 제어방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4592028A (en) * 1982-06-09 1986-05-27 Tokyo Shibaura Denki Kabushiki Kaisha Memory device
JPS59221891A (ja) * 1983-05-31 1984-12-13 Toshiba Corp スタテイツク型半導体記憶装置
JPS62173692A (ja) * 1986-01-28 1987-07-30 Fujitsu Ltd 半導体集積回路
JPS62205596A (ja) * 1986-03-05 1987-09-10 Mitsubishi Electric Corp Ｍｏｓ型メモリ装置の入力バツフア回路
FR2619939B1 (fr) * 1987-09-01 1989-12-08 Thomson Semiconducteurs Circuit de detection de transitions d'adresses
US4922461A (en) * 1988-03-30 1990-05-01 Kabushiki Kaisha Toshiba Static random access memory with address transition detector
JPH01251496A (ja) * 1988-03-31 1989-10-06 Toshiba Corp スタティック型ランダムアクセスメモリ
JPH0748307B2 (ja) * 1989-06-08 1995-05-24 株式会社東芝 半導体メモリ装置
US5003513A (en) * 1990-04-23 1991-03-26 Motorola, Inc. Latching input buffer for an ATD memory

Also Published As

Publication number Publication date
JPH06176575A (ja) 1994-06-24
JP3375143B2 (ja) 2003-02-10
EP0482868B1 (de) 1998-01-07
EP0482868A2 (de) 1992-04-29
EP0482868A3 (en) 1994-11-09
DE69128602D1 (de) 1998-02-12
US5124584A (en) 1992-06-23
KR920009082A (ko) 1992-05-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee