DE69128513T2 - Logische Schaltung mit einer Fehlererfassungsschaltung - Google Patents
Logische Schaltung mit einer FehlererfassungsschaltungInfo
- Publication number
- DE69128513T2 DE69128513T2 DE69128513T DE69128513T DE69128513T2 DE 69128513 T2 DE69128513 T2 DE 69128513T2 DE 69128513 T DE69128513 T DE 69128513T DE 69128513 T DE69128513 T DE 69128513T DE 69128513 T2 DE69128513 T2 DE 69128513T2
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- error detection
- logical
- detection circuit
- logical circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/590,997 US5291075A (en) | 1990-10-01 | 1990-10-01 | Fault detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69128513D1 DE69128513D1 (de) | 1998-02-05 |
DE69128513T2 true DE69128513T2 (de) | 1998-06-25 |
Family
ID=24364609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69128513T Expired - Fee Related DE69128513T2 (de) | 1990-10-01 | 1991-09-30 | Logische Schaltung mit einer Fehlererfassungsschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5291075A (de) |
EP (1) | EP0479515B1 (de) |
JP (1) | JPH04351016A (de) |
DE (1) | DE69128513T2 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5459411A (en) * | 1992-03-26 | 1995-10-17 | Nec Corporation | Wired-OR logic circuits each having a constant current source |
FI97262C (fi) * | 1994-10-03 | 1996-11-11 | Nokia Mobile Phones Ltd | Tulosignaalin kynnysarvon ylityksen virtaa säästävä ilmaisu |
US6104232A (en) * | 1998-08-27 | 2000-08-15 | Maxim Integrated Products | DC output level compensation circuit |
US7955358B2 (en) | 2005-09-19 | 2011-06-07 | Albert Todd J | Bone screw apparatus, system and method |
US9044272B2 (en) | 2009-11-09 | 2015-06-02 | Ebi, Llc | Multiplanar bone anchor system |
US8449578B2 (en) * | 2009-11-09 | 2013-05-28 | Ebi, Llc | Multiplanar bone anchor system |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1251959A (de) * | 1968-02-16 | 1971-11-03 | ||
US3906212A (en) * | 1971-08-18 | 1975-09-16 | Siemens Ag | Series-coupled emitter coupled logic (ECL) circuit having a plurality of independently controllable current paths in a lower plane |
US4286179A (en) * | 1978-10-27 | 1981-08-25 | International Business Machines Corporation | Push pull switch utilizing two current switch circuits |
US4471484A (en) * | 1979-10-18 | 1984-09-11 | Sperry Corporation | Self verifying logic system |
JPS57107637A (en) * | 1980-12-25 | 1982-07-05 | Fujitsu Ltd | Ecl integrated circuit |
US4395767A (en) * | 1981-04-20 | 1983-07-26 | Control Data Corporation | Interconnect fault detector for LSI logic chips |
US4745304A (en) * | 1985-05-03 | 1988-05-17 | Advanced Micro Devices, Inc. | Temperature compensation for ECL circuits |
US4703484A (en) * | 1985-12-19 | 1987-10-27 | Harris Corporation | Programmable integrated circuit fault detection apparatus |
JPH0642627B2 (ja) * | 1986-12-16 | 1994-06-01 | 日本電気株式会社 | 論理回路 |
US4871929A (en) * | 1988-07-07 | 1989-10-03 | Motorola Inc. | ECL logic gate |
US4980579A (en) * | 1988-08-29 | 1990-12-25 | Motorola, Inc. | ECL gate having dummy load for substantially reducing skew |
-
1990
- 1990-10-01 US US07/590,997 patent/US5291075A/en not_active Expired - Lifetime
-
1991
- 1991-09-30 EP EP91308910A patent/EP0479515B1/de not_active Expired - Lifetime
- 1991-09-30 DE DE69128513T patent/DE69128513T2/de not_active Expired - Fee Related
- 1991-10-01 JP JP3278954A patent/JPH04351016A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE69128513D1 (de) | 1998-02-05 |
EP0479515B1 (de) | 1997-12-29 |
JPH04351016A (ja) | 1992-12-04 |
EP0479515A3 (de) | 1994-10-12 |
EP0479515A2 (de) | 1992-04-08 |
US5291075A (en) | 1994-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES L.L.C. (N.D.GE |
|
8328 | Change in the person/name/address of the agent |
Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN |
|
8339 | Ceased/non-payment of the annual fee |