DE69415697D1 - Speicherschaltung mit einer Vielzahl von Eingangsignalen - Google Patents

Speicherschaltung mit einer Vielzahl von Eingangsignalen

Info

Publication number
DE69415697D1
DE69415697D1 DE69415697T DE69415697T DE69415697D1 DE 69415697 D1 DE69415697 D1 DE 69415697D1 DE 69415697 T DE69415697 T DE 69415697T DE 69415697 T DE69415697 T DE 69415697T DE 69415697 D1 DE69415697 D1 DE 69415697D1
Authority
DE
Germany
Prior art keywords
variety
input signals
memory circuit
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69415697T
Other languages
English (en)
Other versions
DE69415697T2 (de
Inventor
Takahiko Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69415697D1 publication Critical patent/DE69415697D1/de
Application granted granted Critical
Publication of DE69415697T2 publication Critical patent/DE69415697T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
DE69415697T 1993-02-03 1994-02-02 Speicherschaltung mit einer Vielzahl von Eingangsignalen Expired - Fee Related DE69415697T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5016010A JP2985554B2 (ja) 1993-02-03 1993-02-03 記憶回路

Publications (2)

Publication Number Publication Date
DE69415697D1 true DE69415697D1 (de) 1999-02-18
DE69415697T2 DE69415697T2 (de) 1999-07-29

Family

ID=11904622

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69415697T Expired - Fee Related DE69415697T2 (de) 1993-02-03 1994-02-02 Speicherschaltung mit einer Vielzahl von Eingangsignalen

Country Status (4)

Country Link
US (1) US5377158A (de)
EP (1) EP0609874B1 (de)
JP (1) JP2985554B2 (de)
DE (1) DE69415697T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5557581A (en) * 1995-04-10 1996-09-17 Sun Microsystems, Inc. Logic and memory circuit with reduced input-to-output signal propagation delay
US6433603B1 (en) 2000-08-14 2002-08-13 Sun Microsystems, Inc. Pulse-based high speed flop circuit
US6420903B1 (en) * 2000-08-14 2002-07-16 Sun Microsystems, Inc. High speed multiple-bit flip-flop
TW200535857A (en) * 2004-04-20 2005-11-01 Innolux Display Corp Dynamic shift register

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151537A (ja) * 1983-01-29 1984-08-30 Toshiba Corp 相補ｍｏｓ形回路
JP2621993B2 (ja) * 1989-09-05 1997-06-18 株式会社東芝 フリップフロップ回路
US5107465A (en) * 1989-09-13 1992-04-21 Advanced Micro Devices, Inc. Asynchronous/synchronous pipeline dual mode memory access circuit and method
JPH0792495B2 (ja) * 1990-06-25 1995-10-09 株式会社東芝 スキャンパス付きフリップフロップ
JPH04121893A (ja) * 1990-09-12 1992-04-22 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0609874B1 (de) 1999-01-07
JPH06230087A (ja) 1994-08-19
EP0609874A2 (de) 1994-08-10
EP0609874A3 (de) 1995-06-07
JP2985554B2 (ja) 1999-12-06
US5377158A (en) 1994-12-27
DE69415697T2 (de) 1999-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee