DE69123794T2 - Unterbrechungssteuerung - Google Patents

Unterbrechungssteuerung

Info

Publication number
DE69123794T2
DE69123794T2 DE69123794T DE69123794T DE69123794T2 DE 69123794 T2 DE69123794 T2 DE 69123794T2 DE 69123794 T DE69123794 T DE 69123794T DE 69123794 T DE69123794 T DE 69123794T DE 69123794 T2 DE69123794 T2 DE 69123794T2
Authority
DE
Germany
Prior art keywords
interrupt control
interrupt
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123794T
Other languages
English (en)
Other versions
DE69123794D1 (de
Inventor
Takashi Miyamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69123794D1 publication Critical patent/DE69123794D1/de
Publication of DE69123794T2 publication Critical patent/DE69123794T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
DE69123794T 1990-07-25 1991-07-23 Unterbrechungssteuerung Expired - Fee Related DE69123794T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2194714A JPH0743653B2 (ja) 1990-07-25 1990-07-25 割込みコントローラ

Publications (2)

Publication Number Publication Date
DE69123794D1 DE69123794D1 (de) 1997-02-06
DE69123794T2 true DE69123794T2 (de) 1997-05-15

Family

ID=16329029

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123794T Expired - Fee Related DE69123794T2 (de) 1990-07-25 1991-07-23 Unterbrechungssteuerung

Country Status (5)

Country Link
US (1) US5410708A (de)
EP (1) EP0468454B1 (de)
JP (1) JPH0743653B2 (de)
KR (1) KR940011670B1 (de)
DE (1) DE69123794T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894577A (en) * 1993-09-22 1999-04-13 Advanced Micro Devices, Inc. Interrupt controller with external in-service indication for power management within a computer system
US6145047A (en) * 1994-05-19 2000-11-07 Vlsi Technology Inc. Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode
US5671421A (en) * 1994-12-07 1997-09-23 Intel Corporation Serial interrupt bus protocol
US5708813A (en) * 1994-12-12 1998-01-13 Digital Equipment Corporation Programmable interrupt signal router
US5943507A (en) * 1994-12-22 1999-08-24 Texas Instruments Incorporated Interrupt routing circuits, systems and methods
US5640571A (en) * 1995-03-01 1997-06-17 Intel Corporation Interrupt steering for a computer system
US5640570A (en) * 1996-01-26 1997-06-17 International Business Machines Corporation Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer
US5815733A (en) * 1996-02-01 1998-09-29 Apple Computer, Inc. System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits
US6070219A (en) * 1996-10-09 2000-05-30 Intel Corporation Hierarchical interrupt structure for event notification on multi-virtual circuit network interface controller
US5819095A (en) * 1996-12-20 1998-10-06 International Business Machines Corporation Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
US5787290A (en) * 1996-12-20 1998-07-28 International Business Machines Corporation Adapter with an onboard interrupt controller for controlling a computer system
DE69731375T2 (de) 1997-06-13 2005-03-17 Alcatel Mehrfachunterbrechungsabwicklungsverfahren und -gerät
US6003109A (en) * 1997-08-15 1999-12-14 Lsi Logic Corporation Method and apparatus for processing interrupts in a data processing system
KR100331028B1 (ko) * 1998-11-18 2002-09-04 한국전자통신연구원 단일신호인터럽트방식의프로세서를위한인터럽트요구제어기및그제어방법
US6493781B1 (en) * 1999-08-19 2002-12-10 Koninklijke Philips Electronics N.V. Servicing of interrupts with stored and restored flags
DE10047183A1 (de) * 2000-09-22 2002-04-18 Infineon Technologies Ag Digitales Zwischenspeicherbauelement
KR100528476B1 (ko) * 2003-07-22 2005-11-15 삼성전자주식회사 컴퓨터 시스템의 인터럽트 처리 장치
US7409483B2 (en) * 2003-12-19 2008-08-05 Intel Corporation Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers
US20050289271A1 (en) * 2004-06-29 2005-12-29 Martinez Alberto J Circuitry to selectively produce MSI signals
JP2006277558A (ja) * 2005-03-30 2006-10-12 Fujitsu Ten Ltd 信号変化検出装置及び信号変化検出方法
US7984281B2 (en) * 2005-10-18 2011-07-19 Qualcomm Incorporated Shared interrupt controller for a multi-threaded processor
US7702889B2 (en) * 2005-10-18 2010-04-20 Qualcomm Incorporated Shared interrupt control method and system for a digital signal processor
US7415557B2 (en) 2006-06-06 2008-08-19 Honeywell International Inc. Methods and system for providing low latency and scalable interrupt collection
JP4897851B2 (ja) * 2009-05-14 2012-03-14 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ・システム及びコンピュータ・システムの制御方法
US8738830B2 (en) 2011-03-03 2014-05-27 Hewlett-Packard Development Company, L.P. Hardware interrupt processing circuit
US9189283B2 (en) 2011-03-03 2015-11-17 Hewlett-Packard Development Company, L.P. Task launching on hardware resource for client
US9645823B2 (en) 2011-03-03 2017-05-09 Hewlett-Packard Development Company, L.P. Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity
JP5588951B2 (ja) * 2011-10-28 2014-09-10 京セラドキュメントソリューションズ株式会社 割り込み制御回路
JP5622284B2 (ja) * 2011-12-28 2014-11-12 京セラドキュメントソリューションズ株式会社 割り込み監視回路
JP6008745B2 (ja) * 2013-01-15 2016-10-19 ルネサスエレクトロニクス株式会社 データ処理装置
JP6582503B2 (ja) * 2015-04-08 2019-10-02 富士通株式会社 情報処理装置
CN111506530A (zh) * 2019-01-30 2020-08-07 智原科技股份有限公司 中断管理系统及其管理方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5549344B2 (de) * 1973-12-19 1980-12-11
US4091447A (en) * 1976-07-19 1978-05-23 Union Carbide Corporation Interrupt control system for a microcomputer
US4080649A (en) * 1976-12-16 1978-03-21 Honeywell Information Systems Inc. Balancing the utilization of I/O system processors
US4177513A (en) * 1977-07-08 1979-12-04 International Business Machines Corporation Task handling apparatus for a computer system
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
IT1193650B (it) * 1983-01-31 1988-07-21 Honeywell Inf Systems Apparato di interruzione ad affidabilita' accresciuta
US4636944A (en) * 1984-01-17 1987-01-13 Concurrent Computer Corporation Multi-level priority micro-interrupt controller
JPS60176145A (ja) * 1984-02-23 1985-09-10 Fujitsu Ltd 割込み処理回路
JPS61183745A (ja) * 1985-02-08 1986-08-16 Mitsubishi Electric Corp 割込制御装置
US4761732A (en) * 1985-11-29 1988-08-02 American Telephone And Telegraph Company, At&T Bell Laboratories Interrupt controller arrangement for mutually exclusive interrupt signals in data processing systems
US5230048A (en) * 1986-09-03 1993-07-20 Wang Laboratories, Inc. Data processing system with tree and list data structure
JPH01246602A (ja) * 1988-03-29 1989-10-02 Mitsubishi Electric Corp プログラマブルコントローラ用特殊機能ユニット
US4862409A (en) * 1988-06-13 1989-08-29 Advanced Micro Devices, Inc. Asynchronous interrupt status bit circuit
JPH0268632A (ja) * 1988-09-05 1990-03-08 Toshiba Corp 割込み制御装置
US5101497A (en) * 1988-09-09 1992-03-31 Compaq Computer Corporation Programmable interrupt controller

Also Published As

Publication number Publication date
EP0468454A3 (en) 1992-05-27
EP0468454A2 (de) 1992-01-29
US5410708A (en) 1995-04-25
JPH0481932A (ja) 1992-03-16
KR940011670B1 (ko) 1994-12-23
EP0468454B1 (de) 1996-12-27
JPH0743653B2 (ja) 1995-05-15
KR920003174A (ko) 1992-02-29
DE69123794D1 (de) 1997-02-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee