DE69120447D1 - Halbleiterspeicheranordnung von dynamischem Typus - Google Patents

Halbleiterspeicheranordnung von dynamischem Typus

Info

Publication number
DE69120447D1
DE69120447D1 DE69120447T DE69120447T DE69120447D1 DE 69120447 D1 DE69120447 D1 DE 69120447D1 DE 69120447 T DE69120447 T DE 69120447T DE 69120447 T DE69120447 T DE 69120447T DE 69120447 D1 DE69120447 D1 DE 69120447D1
Authority
DE
Germany
Prior art keywords
memory device
type semiconductor
semiconductor memory
dynamic type
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120447T
Other languages
English (en)
Other versions
DE69120447T2 (de
Inventor
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69120447D1 publication Critical patent/DE69120447D1/de
Publication of DE69120447T2 publication Critical patent/DE69120447T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
DE69120447T 1990-03-30 1991-03-26 Halbleiterspeicheranordnung von dynamischem Typus Expired - Fee Related DE69120447T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02084609A JP3101297B2 (ja) 1990-03-30 1990-03-30 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69120447D1 true DE69120447D1 (de) 1996-08-01
DE69120447T2 DE69120447T2 (de) 1996-12-05

Family

ID=13835437

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120447T Expired - Fee Related DE69120447T2 (de) 1990-03-30 1991-03-26 Halbleiterspeicheranordnung von dynamischem Typus

Country Status (5)

Country Link
US (1) US5323345A (de)
EP (1) EP0449204B1 (de)
JP (1) JP3101297B2 (de)
KR (1) KR940004515B1 (de)
DE (1) DE69120447T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940007639B1 (ko) * 1991-07-23 1994-08-22 삼성전자 주식회사 분할된 입출력 라인을 갖는 데이타 전송회로
KR940007640B1 (ko) * 1991-07-31 1994-08-22 삼성전자 주식회사 공통 입출력선을 가지는 데이타 전송회로
US5283760A (en) * 1991-08-14 1994-02-01 Samsung Electronics Co., Ltd. Data transmission circuit
EP0579862A1 (de) * 1992-07-24 1994-01-26 Siemens Aktiengesellschaft Integrierte Halbleiterspeicheranordnung
US5539701A (en) * 1994-08-05 1996-07-23 Nippon Steel Corporation Sense circuit for semiconductor memory devices
TW299448B (de) * 1995-07-20 1997-03-01 Matsushita Electric Ind Co Ltd
KR0164359B1 (ko) * 1995-09-06 1999-02-18 김광호 싸이클시간을 감소시키기 위한 반도체 메모리 장치
DE19536486C2 (de) * 1995-09-29 1997-08-07 Siemens Ag Bewerter- und Verstärkerschaltung
KR0153602B1 (ko) * 1995-10-04 1998-12-01 김광호 반도체 메모리 장치의 데이타 고속 전송회로
JP2000132969A (ja) 1998-10-28 2000-05-12 Nec Corp ダイナミックメモリ装置
JP2001006367A (ja) * 1999-06-21 2001-01-12 Mitsubishi Electric Corp 半導体記憶装置
JP2004095017A (ja) * 2002-08-30 2004-03-25 Fujitsu Ltd センスアンプ
CN100354971C (zh) 2002-11-08 2007-12-12 株式会社日立制作所 半导体存储装置
JP2004213830A (ja) * 2003-01-08 2004-07-29 Sony Corp 半導体記憶装置
KR100546373B1 (ko) * 2003-08-28 2006-01-26 삼성전자주식회사 기준셀을 사용하지 않는 ｖｓｓ／ｖｄｄ 비트라인프리차지 스킴을 갖는 반도체 메모리장치
KR100753418B1 (ko) * 2006-03-30 2007-08-30 주식회사 하이닉스반도체 로우 및 컬럼 어드레스를 이용하여 비트라인 감지 증폭동작을 제어하는 반도체 메모리 장치

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132930A (en) * 1986-07-31 1992-07-21 Mitsubishi Denki Kabushiki Kaisha CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines
JPS63175293A (ja) * 1987-01-16 1988-07-19 Hitachi Ltd ダイナミツク型ｒａｍ
JPH0799627B2 (ja) * 1987-01-23 1995-10-25 松下電器産業株式会社 半導体メモリの書き込み読み出し回路
JPS63183687A (ja) * 1987-01-26 1988-07-29 Hitachi Ltd 半導体記憶装置
JPS6414792A (en) * 1987-07-08 1989-01-18 Hitachi Ltd Semiconductor storage device
JPH07105137B2 (ja) * 1987-11-17 1995-11-13 日本電気株式会社 半導体メモリ
JPH01199393A (ja) * 1988-02-03 1989-08-10 Mitsubishi Electric Corp 半導体記憶装置
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
JPH01173392A (ja) * 1987-12-28 1989-07-10 Toshiba Corp 半導体記憶装置
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH01264692A (ja) * 1988-04-15 1989-10-20 Hitachi Ltd 半導体メモリ回路
JPH0214487A (ja) * 1988-06-30 1990-01-18 Mitsubishi Electric Corp 半導体記憶装置
US5023842A (en) * 1988-07-11 1991-06-11 Kabushiki Kaisha Toshiba Semiconductor memory having improved sense amplifiers
JP2681285B2 (ja) * 1988-09-19 1997-11-26 富士通株式会社 半導体記憶装置
US5146427A (en) * 1989-08-30 1992-09-08 Hitachi Ltd. High speed semiconductor memory having a direct-bypass signal path

Also Published As

Publication number Publication date
EP0449204B1 (de) 1996-06-26
EP0449204A2 (de) 1991-10-02
KR940004515B1 (ko) 1994-05-25
JPH03283186A (ja) 1991-12-13
JP3101297B2 (ja) 2000-10-23
EP0449204A3 (de) 1994-01-05
US5323345A (en) 1994-06-21
DE69120447T2 (de) 1996-12-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee