DE69115082D1 - Halbleitervorrichtung mit vielschichtiger Verdrahtungsstruktur und Verfahren zu ihrer Herstellung. - Google Patents

Halbleitervorrichtung mit vielschichtiger Verdrahtungsstruktur und Verfahren zu ihrer Herstellung.

Info

Publication number
DE69115082D1
DE69115082D1 DE69115082T DE69115082T DE69115082D1 DE 69115082 D1 DE69115082 D1 DE 69115082D1 DE 69115082 T DE69115082 T DE 69115082T DE 69115082 T DE69115082 T DE 69115082T DE 69115082 D1 DE69115082 D1 DE 69115082D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
same
wiring structure
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115082T
Other languages
English (en)
Other versions
DE69115082T2 (de
Inventor
Fumitomo Matsuoka
Naoki Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69115082D1 publication Critical patent/DE69115082D1/de
Application granted granted Critical
Publication of DE69115082T2 publication Critical patent/DE69115082T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69115082T 1990-03-02 1991-03-01 Halbleitervorrichtung mit vielschichtiger Verdrahtungsstruktur und Verfahren zu ihrer Herstellung. Expired - Fee Related DE69115082T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4950090 1990-03-02
JP3112658A JPH04226054A (ja) 1990-03-02 1991-02-20 多層配線構造を有する半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69115082D1 true DE69115082D1 (de) 1996-01-18
DE69115082T2 DE69115082T2 (de) 1996-05-15

Family

ID=26389898

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115082T Expired - Fee Related DE69115082T2 (de) 1990-03-02 1991-03-01 Halbleitervorrichtung mit vielschichtiger Verdrahtungsstruktur und Verfahren zu ihrer Herstellung.

Country Status (4)

Country Link
US (2) US5462893A (de)
EP (1) EP0444695B1 (de)
JP (1) JPH04226054A (de)
DE (1) DE69115082T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321211A (en) * 1992-04-30 1994-06-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit via structure
JPH06104341A (ja) * 1992-09-18 1994-04-15 Toshiba Corp 半導体集積回路およびその製造方法
US5471094A (en) * 1994-02-24 1995-11-28 Integrated Device Technology, Inc. Self-aligned via structure
JP2616706B2 (ja) * 1994-08-04 1997-06-04 日本電気株式会社 半導体装置およびその製造方法
US5736457A (en) 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US5757077A (en) * 1995-02-03 1998-05-26 National Semiconductor Corporation Integrated circuits with borderless vias
US5858875A (en) * 1995-02-03 1999-01-12 National Semiconductor Corporation Integrated circuits with borderless vias
US5656543A (en) * 1995-02-03 1997-08-12 National Semiconductor Corporation Fabrication of integrated circuits with borderless vias
US5619072A (en) * 1995-02-09 1997-04-08 Advanced Micro Devices, Inc. High density multi-level metallization and interconnection structure
US5759867A (en) * 1995-04-21 1998-06-02 International Business Machines Corporation Method of making a disposable corner etch stop-spacer for borderless contacts
US5547892A (en) * 1995-04-27 1996-08-20 Taiwan Semiconductor Manufacturing Company Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors
US5654231A (en) * 1996-03-25 1997-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of eliminating buried contact trench in SRAM technology
US5756396A (en) * 1996-05-06 1998-05-26 Taiwan Semiconductor Manufacturing Company Ltd Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
JP3068462B2 (ja) * 1996-05-29 2000-07-24 日本電気株式会社 半導体装置の製造方法
US5869393A (en) * 1996-06-19 1999-02-09 Vanguard International Semiconductor Corp. Method for fabricating multi-level interconnection
US5891805A (en) * 1996-12-13 1999-04-06 Intel Corporation Method of forming contacts
JP2897827B2 (ja) 1997-04-08 1999-05-31 日本電気株式会社 半導体装置の多層配線構造
US6074943A (en) * 1997-04-16 2000-06-13 Texas Instruments Incorporated Sidewalls for guiding the via etch
WO1999000840A1 (en) * 1997-06-26 1999-01-07 Advanced Micro Devices, Inc. Interconnect spacer structures
US6015751A (en) * 1998-04-06 2000-01-18 Taiwan Semiconductor Manufacturing Company Self-aligned connection to underlayer metal lines through unlanded via holes
US6214737B1 (en) * 1999-01-20 2001-04-10 Advanced Micro Devices, Inc. Simplified sidewall formation for sidewall patterning of sub 100 nm structures
US7482278B1 (en) 1999-02-11 2009-01-27 Taiwan Semiconductor Manufacturing Co., Ltd. Key-hole free process for high aspect ratio gap filling with reentrant spacer
CA2826823A1 (en) 2011-02-11 2012-08-16 Halliburton Energy Services, Inc. Broadband flex joint isolator for acoustic tools

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433004A (en) * 1979-07-11 1984-02-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and a method for manufacturing the same
JPS58137231A (ja) * 1982-02-09 1983-08-15 Nec Corp 集積回路装置
JPS59154040A (ja) * 1983-02-22 1984-09-03 Toshiba Corp 半導体装置の製造方法
JPS59200439A (ja) * 1983-04-27 1984-11-13 Toshiba Corp 半導体装置の製造方法
JPS6080264A (ja) * 1983-10-07 1985-05-08 Toshiba Corp 半導体装置
JPS60115245A (ja) * 1983-11-28 1985-06-21 Toshiba Corp 半導体装置の製造方法
JPS60115221A (ja) * 1983-11-28 1985-06-21 Toshiba Corp 半導体装置の製造方法
US4807013A (en) * 1984-10-17 1989-02-21 American Telephone And Telegraph Company At&T Bell Laboratories Polysilicon fillet
JPS6196734A (ja) * 1984-10-17 1986-05-15 アメリカン　テレフォン　アンド　テレグラフ　カムパニー ポリシリコン　フイレツト
JPS6450443A (en) * 1987-08-20 1989-02-27 Toshiba Corp Semiconductor device
JPH02222148A (ja) * 1989-02-22 1990-09-04 Yamaha Corp 半導体装置
US4931353A (en) * 1989-03-01 1990-06-05 The Boeing Company Structure and method for selectively producing a conductive region on a substrate
US4933303A (en) * 1989-07-25 1990-06-12 Standard Microsystems Corporation Method of making self-aligned tungsten interconnection in an integrated circuit
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same

Also Published As

Publication number Publication date
EP0444695A2 (de) 1991-09-04
EP0444695A3 (en) 1992-04-15
DE69115082T2 (de) 1996-05-15
JPH04226054A (ja) 1992-08-14
US5543360A (en) 1996-08-06
EP0444695B1 (de) 1995-12-06
US5462893A (en) 1995-10-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee