JPS6080264A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6080264A
JPS6080264A JP58187927A JP18792783A JPS6080264A JP S6080264 A JPS6080264 A JP S6080264A JP 58187927 A JP58187927 A JP 58187927A JP 18792783 A JP18792783 A JP 18792783A JP S6080264 A JPS6080264 A JP S6080264A
Authority
JP
Japan
Prior art keywords
substrate
film
wiring layer
wiring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58187927A
Other languages
English (en)
Inventor
Tetsuya Iizuka
飯塚　哲哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58187927A priority Critical patent/JPS6080264A/ja
Priority to US06/638,782 priority patent/US4646126A/en
Publication of JPS6080264A publication Critical patent/JPS6080264A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体基体上に集積回路（ＩＣ）チップを搭
載した半導体装置に関する。
〔発明の技術的背景とその問題点〕
従来、システムを構成する高密度の印刷配線板として、
例えばセラミック基板上に金の配線を印刷したものが知
られている。しかしながら１こうした印刷配線板によれ
ば、セラミック基板を用いているためコスト高であると
ともに、配線モ数百ミクロンピッチという非常に密度が
低いという欠点を有する。また、配線の督度が低いため
、配線長が長くなり、浮遊容量が大きく高速化できない
という欠点を有する。
このようなことから、こうした欠点を克服するために、
通常一種類の集積回路（ＩＣ）チップ多数個を半導体基
板（ウェーッ・）上に形成するところを、ウェノ＼上に
異なる機能のチップあるいは回路プロ、りとそれを結ぶ
配線とを形成する試みが行われている。しかるに、かか
る試みにより、配線の密度が上シ、高速化を図ることが
できる。しかしながら、欠陥等により動作しない回路ブ
ロックが生じた場合、ウェハ全体を不良品とせざるを得
ない。そこで、これを改善するために、上述した主とな
る回路ブロックとは別に冗長な回路ブロックを設け、主
となる回路ブロックが不良等により使用できないとき、
不良の回路ブロックと切りかえる方法がとられている。
しかしながら、こうした方法では充分な歩留シが得られ
ることが少なく、また冗長回路に伴なう速度の低下があ
るため実用化に至っていない。
〔発明の目的〕
本発明は上ａピ事情に録みてなさ瓦たもので、低コスト
化、高速化並びに素子の高集積化を図った半導体装置を
提供する仁とを目的とするものである。
〔発明の概要〕
本発明は、半専体基体上に試験評価済みの集積回路チッ
プを搭載し、同基体上に絶縁層を介して配線層及び前記
チップに接続するパッドを設けることによって、前述し
た目的を達成すること全骨子とする。
〔発明の実施例〕
以下、本発明の一実施例を第１図及び第２図を参照して
説明する。
図中の１は、半導体基体としての高不純物濃度のＳｔ基
板である。ここで、基板１は低抵抗で、例えば接地電位
や５ｖなどの電源電位に・ぐイアスされている。この基
板１上には、第１〜第３の５ｌＯ２膜２１〜２３が順に
形成され、これらＳ　ｉ　Ｏ２膜２１〜２３０所定領域
には別途試験評価された集積回路（ＩＣ）チン７″３・
・・を搭載すべき大きな開口部４が設けられている。こ
のチンｆ３は、導電性の接着剤層５を介して基板１上に
搭載されている。なお、接着剤層５０代りにＡｕＳｉな
どを用いてアロイを形成して固定してもよく、ξうする
ことによシチンプ３から発生する熱を基板１へ逃がすこ
とができる。前記第１０ｓ＋ｏ２Ｈ２１上には、配線層
６が垂１１方向に形成されている。なお、前記５ｔＯ２
膜２１　はその膜厚が厚いため、配線層６・・・を信号
配線として用いた場合、浮遊容量が小さくなる。前記Ｓ
　ｒ　０２膜２！の一部分は他の領域と比べて薄くなっ
ておシ、この薄膜化された５ｉ０２Ｎ　２１上に例えば
多結晶シリコンからなる配線層７が形成されている。配
線層７は配線層６と同一の層を用いてもよい。ここで、
この配線層７と薄膜化されたＳ　ＩＯ２膜２凰と高不純
物濃度のＳｔ基基板圧よシ、電源と結合した容量が形成
され、例えば配線層７を電源線に用いれば電源線のノイ
ズを低減するだめのフィルターコンデンサとして用いら
れる。前記第２のＳｉＯ，Ｊ　ｚ、の前記配線層６の一
部に対応する部分及び他の領域には、夫々コンタクトホ
ール８・・・、９・・・が形成されている。同第２の８
１０２膜２２上には、前記チップ３・・・とデンディン
グワイヤ１０・・・を介して接続するＡノからなるパッ
ド１ノ・・・が、チップ３・・・の周囲に設けられてい
るとともに、・（ラド１）・・・に夫々接続する例えば
Ａｔからなる配線層１２・・・が水−・ｉζ方回に形成
されている。ここで、互いに交差する前記配？ＩＭ６・
・・。
１２・・・ハ、適宜コンタクトホール９・・・を介して
接続されている。また、配置面層１２・・・は、前記コ
ンタクトホール８・・・を介して第１の５ｉ０２膜２１
上の一部の配置１ｉｔｉ１層６・・・と接続している。
前記・ぐラド１ノ・・・に対応する第３の５ｉ０２膜　
２３には、７ｔンデイングワイヤ９・・・の取り出しの
ためにυ；】口部１３・・・が設けられている。
しかして、本発明によれば、以下に示す種々の効果を有
する。
■　従来の如く、下地層としてセラミ、ｙり基板を用い
ずにＳｉ基板１を用いるため、コス）ｋ低減できる。
（リ　集積回路技術をそのまま用いて、基板１上の第１
の８１０□Ｍ２１上に配線層６・・・を形成するため、
平面度が極めてよいとともに、現在の技術レベルで１〜
２μｍ程度の細い配線巾及び間隔が実現できる。
■　前述の如く、細い配線中及び間隔が実現できること
にょシ、配線部分の容量が小さくな　のり、これをドラ
イ！するバッファーを従来程大　３きくとらずに高速化
できる。また、配線層６・・・　４の長さそのものも短
かくなるので、光速伝播に相当する遅延も短縮される。
　場 ■　電諒電線にと９つけるフィルターコンデ　るンサー
もチン７°３・・・に近接した部分に設けると　きとが
できるため、インダクタンス成分が小さく　シ効果の高
いフィルターリングができ、電源線のノイズを低減でき
る。　板 ■　搭載されるＩＣＣチラノは予め試験を終　ず了した
ものであるとともに、主として配線層　形６・・・、１
２・・・のみである基板部は高歩留りであ　〔るため、
全体として極めて高い歩留りが達成でき、コスト低減が
可能である。　化 なお、本発明に係る半導体装置は、上記実施　４例のも
のに限らず、第３図に示す如くＩＣチチン　。２図）２
１がＳｔ基板１上に絶縁膜２２にょシ絶縁された状態で
搭載された構造のものでもよい。か　のかる構造の場合
、チップ２１と基板１との夫々　面電位を異にすること
ができる。なお、図中の１．３２は第１層目の配線層を
示し、４ノ。
２は第２層の配Ｎ、！；７層を夫々示す。
また、上記実施例では、配線層が２層構造の合について
述べたが、これに限らず、１層ありは３層以上の構造の
場合でも同様に適用でる。なお、配線層の材料がＡｔも
しくは多結晶リコンに限らないのは勿論のことである。
更に、上記実施例では半導体基体としてＳｔ基全用いた
場合について述べたが、これに限ら、ザファイア等の絶
縁性基板上に半導体層を成した構造のものでもよい。
発明の効果〕 以上詳述した如く本発明によれば、低コスト、高速化並
びに高集積化した信頼性の高い半休装置を提供できるも
のである。
面の簡単な説明 第１図は本発明の一実施例に係る半導体装置平面図、第
２図は第１図のＸ　−Ｘ線に漕う断固、第３図は本発明
の他の実施例に係る半導体装置の断面図である。
１・・・Ｓｉ基板（半導体基板）、２１〜２３・・・Ｓ
ｉＯ□膜（絶縁膜）３，２１・・・集積回路チップ、４
゜１３・・・開口部、５・・・導電性の接着剤層、６，
７゜Ｊ２，３１．３２９４１．４２・・・配線層、８゜
９・・・コンタクトホール、１０・・・ビンディングワ
イヤ、１ノ・・・／にラド。

Claims (4)

    【特許請求の範囲】
  1. （１）半導体基体と、この基体上に搭載された試験評価
    済みの集積回路チップと、同基体上に絶縁膜を介して設
    けられた配線層、及び前記チップに接続する・ぐラドと
    を具備することを特徴とする半導体装置。
  2. （２）　半導体基体が不純物を高良度に含むとともに、
    配線層下の絶縁膜部分が他の部分より薄膜化されて容量
    素子を形成することを特徴とする特許請求の範囲第１項
    記載の半導体装置。
  3. （３）試験評価済みの集積回路チップが半導体基体上に
    電気的に接続された状態で搭載されていることを特徴と
    する特許請求の範囲第１項記載の半導体装置。
  4. （４）試験評価済みの集積回路チップが半導体基体上に
    絶縁された状態で搭載されていることを特徴とする特許
    請求の範囲第１項記載の半導体装置。
JP58187927A 1983-10-07 1983-10-07 半導体装置 Pending JPS6080264A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58187927A JPS6080264A (ja) 1983-10-07 1983-10-07 半導体装置
US06/638,782 US4646126A (en) 1983-10-07 1984-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58187927A JPS6080264A (ja) 1983-10-07 1983-10-07 半導体装置

Publications (1)

Publication Number Publication Date
JPS6080264A true JPS6080264A (ja) 1985-05-08

Family

ID=16214631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58187927A Pending JPS6080264A (ja) 1983-10-07 1983-10-07 半導体装置

Country Status (2)

Country Link
US (1) US4646126A (ja)
JP (1) JPS6080264A (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4858175A (en) * 1984-09-29 1989-08-15 Kabushiki Kaisha Toshiba Monolithic semi-custom IC having standard LSI sections and coupling gate array sections
JPS6334955A (ja) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US4868634A (en) * 1987-03-13 1989-09-19 Citizen Watch Co., Ltd. IC-packaged device
NL8701997A (nl) * 1987-08-26 1989-03-16 Philips Nv Geintegreerde halfgeleiderschakeling met ontkoppelde dc bedrading.
JPS6481343A (en) * 1987-09-24 1989-03-27 Nec Corp Manufacture of integrated circuit
JPH0797602B2 (ja) * 1988-05-06 1995-10-18 日本電気株式会社 半導体集積回路装置
US4998160A (en) * 1989-01-23 1991-03-05 Motorola, Inc. Substrate power supply contact for power integrated circuits
NL8900989A (nl) * 1989-04-20 1990-11-16 Philips Nv Halfgeleiderinrichting met een in een kunststof omhulling ingebed halfgeleiderlichaam.
US5293073A (en) * 1989-06-27 1994-03-08 Kabushiki Kaisha Toshiba Electrode structure of a semiconductor device which uses a copper wire as a bonding wire
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
US5061987A (en) * 1990-01-09 1991-10-29 Northrop Corporation Silicon substrate multichip assembly
JPH04226054A (ja) * 1990-03-02 1992-08-14 Toshiba Corp 多層配線構造を有する半導体装置及びその製造方法
JP2007059867A (ja) * 2005-07-26 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5145978A (ja) * 1974-08-19 1976-04-19 Ibm
JPS5613474A (en) * 1979-04-30 1981-02-09 Kollmorgen Tech Corp Immobilization of surface of metal apparatus in electroless copper precipitation method

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3256465A (en) * 1962-06-08 1966-06-14 Signetics Corp Semiconductor device assembly with true metallurgical bonds
US3619731A (en) * 1968-10-11 1971-11-09 Rca Corp Multiple pellet semiconductor device
US3908187A (en) * 1973-01-02 1975-09-23 Gen Electric High voltage power transistor and method for making
US4083063A (en) * 1973-10-09 1978-04-04 General Electric Company Gate turnoff thyristor with a pilot scr
US4023197A (en) * 1974-04-15 1977-05-10 Ibm Corporation Integrated circuit chip carrier and method for forming the same
JPS5329551B2 (ja) * 1974-08-19 1978-08-22
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US4122479A (en) * 1975-01-31 1978-10-24 Hitachi, Ltd. Optoelectronic device having control circuit for light emitting element and circuit for light receiving element integrated in a semiconductor body
US4143385A (en) * 1976-09-30 1979-03-06 Hitachi, Ltd. Photocoupler
JPS5351985A (en) * 1976-10-22 1978-05-11 Hitachi Ltd Semiconductor wiring constitution
JPS5586144A (en) * 1978-12-25 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
US4285001A (en) * 1978-12-26 1981-08-18 Board Of Trustees Of Leland Stanford Jr. University Monolithic distributed resistor-capacitor device and circuit utilizing polycrystalline semiconductor material
US4380114A (en) * 1979-04-11 1983-04-19 Teccor Electronics, Inc. Method of making a semiconductor switching device
JPS5928056B2 (ja) * 1979-12-26 1984-07-10 三菱電機株式会社 半導体集積回路の製造方法
JPS58154254A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5145978A (ja) * 1974-08-19 1976-04-19 Ibm
JPS5613474A (en) * 1979-04-30 1981-02-09 Kollmorgen Tech Corp Immobilization of surface of metal apparatus in electroless copper precipitation method

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