DE69114554T2 - Halbleiteranordnung des Harzverkapselungstyps. - Google Patents

Halbleiteranordnung des Harzverkapselungstyps.

Info

Publication number
DE69114554T2
DE69114554T2 DE69114554T DE69114554T DE69114554T2 DE 69114554 T2 DE69114554 T2 DE 69114554T2 DE 69114554 T DE69114554 T DE 69114554T DE 69114554 T DE69114554 T DE 69114554T DE 69114554 T2 DE69114554 T2 DE 69114554T2
Authority
DE
Germany
Prior art keywords
semiconductor device
type semiconductor
resin encapsulation
encapsulation type
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114554T
Other languages
English (en)
Other versions
DE69114554D1 (de
Inventor
Kazuichi Komenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69114554D1 publication Critical patent/DE69114554D1/de
Application granted granted Critical
Publication of DE69114554T2 publication Critical patent/DE69114554T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
DE69114554T 1990-03-13 1991-03-12 Halbleiteranordnung des Harzverkapselungstyps. Expired - Fee Related DE69114554T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2062037A JPH0760837B2 (ja) 1990-03-13 1990-03-13 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
DE69114554D1 DE69114554D1 (de) 1995-12-21
DE69114554T2 true DE69114554T2 (de) 1996-05-02

Family

ID=13188570

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114554T Expired - Fee Related DE69114554T2 (de) 1990-03-13 1991-03-12 Halbleiteranordnung des Harzverkapselungstyps.

Country Status (4)

Country Link
US (1) US5089879A (de)
EP (1) EP0447922B1 (de)
JP (1) JPH0760837B2 (de)
DE (1) DE69114554T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2538717B2 (ja) * 1990-04-27 1996-10-02 株式会社東芝 樹脂封止型半導体装置
ATE186795T1 (de) * 1990-07-21 1999-12-15 Mitsui Chemicals Inc Halbleiteranordnung mit einer packung
JP2501953B2 (ja) * 1991-01-18 1996-05-29 株式会社東芝 半導体装置
JPH05144992A (ja) * 1991-11-18 1993-06-11 Mitsubishi Electric Corp 半導体装置およびその製造方法ならびにその製造に使用されるリードフレームおよびその製造方法
JPH05206354A (ja) * 1992-01-24 1993-08-13 Mitsubishi Electric Corp 半導体圧力センサおよびその製造方法
JP2866572B2 (ja) * 1994-02-07 1999-03-08 三菱電機株式会社 半導体製造方法
JP3462921B2 (ja) * 1995-02-14 2003-11-05 三菱電機株式会社 半導体装置
EP0887850A3 (de) 1997-06-23 2001-05-02 STMicroelectronics, Inc. Erzeugung eines Leiterrahmens mit verbesserten thermischen Eigenschaften
US20030151120A1 (en) * 2000-06-28 2003-08-14 Hundt Michael J. Lead-frame forming for improved thermal performance
US20040109525A1 (en) * 2002-12-09 2004-06-10 Chieng Koc Vai Chieng Aka Michael Automatic chip counting system (process)
US20090278762A1 (en) * 2008-05-09 2009-11-12 Viasat, Inc. Antenna Modular Sub-array Super Component
US8120537B2 (en) * 2008-05-09 2012-02-21 Viasat, Inc. Inclined antenna systems and methods
CN102515082A (zh) * 2011-12-31 2012-06-27 天水华天科技股份有限公司 一种单载体mems器件封装件及其生产方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011462B2 (ja) * 1977-01-31 1985-03-26 日本電気株式会社 半導体装置
JPS58207657A (ja) * 1982-05-28 1983-12-03 Fujitsu Ltd 半導体装置及びその製造方法
JPS6080230A (ja) * 1983-10-07 1985-05-08 Akita Denshi Kk 半導体装置およびその製法
US4814943A (en) * 1986-06-04 1989-03-21 Oki Electric Industry Co., Ltd. Printed circuit devices using thermoplastic resin cover plate
JPS63169051A (ja) * 1987-01-05 1988-07-13 Nec Corp 半導体装置
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
US4985751A (en) * 1988-09-13 1991-01-15 Shin-Etsu Chemical Co., Ltd. Resin-encapsulated semiconductor devices

Also Published As

Publication number Publication date
US5089879A (en) 1992-02-18
JPH0760837B2 (ja) 1995-06-28
JPH03263334A (ja) 1991-11-22
EP0447922B1 (de) 1995-11-15
EP0447922A1 (de) 1991-09-25
DE69114554D1 (de) 1995-12-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee