DE69023745D1 - Oberflächenstruktur eines Keramiksubstrates und Verfahren zu deren Herstellung. - Google Patents

Oberflächenstruktur eines Keramiksubstrates und Verfahren zu deren Herstellung.

Info

Publication number
DE69023745D1
DE69023745D1 DE69023745T DE69023745T DE69023745D1 DE 69023745 D1 DE69023745 D1 DE 69023745D1 DE 69023745 T DE69023745 T DE 69023745T DE 69023745 T DE69023745 T DE 69023745T DE 69023745 D1 DE69023745 D1 DE 69023745D1
Authority
DE
Germany
Prior art keywords
production
ceramic substrate
surface structure
ceramic
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023745T
Other languages
English (en)
Other versions
DE69023745T2 (de
Inventor
Akira Yamakawa
Akira Sasame
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Publication of DE69023745D1 publication Critical patent/DE69023745D1/de
Application granted granted Critical
Publication of DE69023745T2 publication Critical patent/DE69023745T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12889—Au-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12944—Ni-base component

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
DE69023745T 1989-12-07 1990-12-05 Oberflächenstruktur eines Keramiksubstrates und Verfahren zu deren Herstellung. Expired - Fee Related DE69023745T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1318250A JP2760107B2 (ja) 1989-12-07 1989-12-07 セラミックス基板の表面構造およびその製造方法

Publications (2)

Publication Number Publication Date
DE69023745D1 true DE69023745D1 (de) 1996-01-04
DE69023745T2 DE69023745T2 (de) 1996-07-25

Family

ID=18097111

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023745T Expired - Fee Related DE69023745T2 (de) 1989-12-07 1990-12-05 Oberflächenstruktur eines Keramiksubstrates und Verfahren zu deren Herstellung.

Country Status (6)

Country Link
US (1) US5134461A (de)
EP (1) EP0431606B1 (de)
JP (1) JP2760107B2 (de)
CA (1) CA2031459C (de)
DE (1) DE69023745T2 (de)
HK (1) HK174996A (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5190601A (en) * 1989-12-07 1993-03-02 Sumitomo Electric Industries, Ltd. Surface structure of ceramics substrate and method of manufacturing the same
US5317190A (en) * 1991-10-25 1994-05-31 International Business Machines Corporation Oxygen assisted ohmic contact formation to N-type gallium arsenide
JP3575068B2 (ja) * 1994-08-02 2004-10-06 住友電気工業株式会社 平滑なめっき層を有するセラミックスメタライズ基板およびその製造方法
JP3000877B2 (ja) * 1995-02-20 2000-01-17 松下電器産業株式会社 金メッキ電極の形成方法、基板及びワイヤボンディング方法
US5744752A (en) * 1995-06-05 1998-04-28 International Business Machines Corporation Hermetic thin film metallized sealband for SCM and MCM-D modules
JP3022765B2 (ja) * 1996-03-27 2000-03-21 日本電気株式会社 半導体装置及び半導体素子の実装方法
JP3239231B2 (ja) * 1996-04-11 2001-12-17 日本特殊陶業株式会社 パッドを備えるセラミック基板、端子部材を備えるセラミック基板およびそれらの製造方法
US6225569B1 (en) 1996-11-15 2001-05-01 Ngk Spark Plug Co., Ltd. Wiring substrate and method of manufacturing the same
CA2313438C (en) 2000-07-06 2003-03-11 B-Con Engineering Inc. High quality optical surface and method of producing same
DE10311031B4 (de) * 2003-03-13 2005-04-21 Siemens Ag Elektrochemischer Sensor und Verfahren zu dessen Herstellung

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1027525A (de) * 1962-03-02
JPS5032020A (de) * 1973-07-24 1975-03-28
JPS531858A (en) * 1976-06-29 1978-01-10 Kokusai Electric Co Ltd Method of forming thin film circuit
JPS59114846A (ja) * 1982-12-21 1984-07-03 Narumi China Corp 半導体塔載用セラミツクパツケ−ジ
JPS6056073A (ja) * 1983-09-05 1985-04-01 Hitachi Ltd セラミツク基板への部分厚付け金被覆方法
JP2579315B2 (ja) * 1987-06-17 1997-02-05 新光電気工業株式会社 セラミツクパツケ−ジ
JP2529294B2 (ja) * 1987-09-25 1996-08-28 株式会社日立製作所 多層めつき方法
KR920005459B1 (ko) * 1988-08-30 1992-07-04 가부시기가이샤 히다찌세이사꾸쇼 금속의 균질화방법 및 회로기판

Also Published As

Publication number Publication date
CA2031459C (en) 1996-01-23
EP0431606B1 (de) 1995-11-22
CA2031459A1 (en) 1991-06-08
EP0431606A3 (en) 1993-01-27
US5134461A (en) 1992-07-28
JP2760107B2 (ja) 1998-05-28
JPH03179793A (ja) 1991-08-05
HK174996A (en) 1996-09-27
EP0431606A2 (de) 1991-06-12
DE69023745T2 (de) 1996-07-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee