DE69031394D1 - Verfahren zum Herstellen eines keramischen Mehrschichtsubstrates - Google Patents

Verfahren zum Herstellen eines keramischen Mehrschichtsubstrates

Info

Publication number
DE69031394D1
DE69031394D1 DE69031394T DE69031394T DE69031394D1 DE 69031394 D1 DE69031394 D1 DE 69031394D1 DE 69031394 T DE69031394 T DE 69031394T DE 69031394 T DE69031394 T DE 69031394T DE 69031394 D1 DE69031394 D1 DE 69031394D1
Authority
DE
Germany
Prior art keywords
manufacturing
ceramic substrate
multilayer ceramic
multilayer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031394T
Other languages
English (en)
Inventor
Kazuaki Satou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69031394D1 publication Critical patent/DE69031394D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081—Compound repelling a metal, e.g. solder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Multi-Conductor Connections (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
DE69031394T 1989-01-24 1990-01-23 Verfahren zum Herstellen eines keramischen Mehrschichtsubstrates Expired - Lifetime DE69031394D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1013211A JPH0632367B2 (ja) 1989-01-24 1989-01-24 セラミック基板のｉ／ｏパッドの形成方法

Publications (1)

Publication Number Publication Date
DE69031394D1 true DE69031394D1 (de) 1997-10-16

Family

ID=11826821

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031394T Expired - Lifetime DE69031394D1 (de) 1989-01-24 1990-01-23 Verfahren zum Herstellen eines keramischen Mehrschichtsubstrates

Country Status (5)

Country Link
US (1) US5061552A (de)
EP (1) EP0380289B1 (de)
JP (1) JPH0632367B2 (de)
CA (1) CA2008284C (de)
DE (1) DE69031394D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436412A (en) * 1992-10-30 1995-07-25 International Business Machines Corporation Interconnect structure having improved metallization
TW253856B (en) * 1994-12-13 1995-08-11 At & T Corp Method of solder bonding, and article produced by the method
US6300678B1 (en) 1997-10-03 2001-10-09 Fujitsu Limited I/O pin having solder dam for connecting substrates
US6037044A (en) 1998-01-08 2000-03-14 International Business Machines Corporation Direct deposit thin film single/multi chip module
US6902098B2 (en) * 2001-04-23 2005-06-07 Shipley Company, L.L.C. Solder pads and method of making a solder pad
US20050056458A1 (en) * 2003-07-02 2005-03-17 Tsuyoshi Sugiura Mounting pad, package, device, and method of fabricating the device
FI123205B (fi) * 2008-05-12 2012-12-31 Imbera Electronics Oy Piirimoduuli ja menetelmä piirimoduulin valmistamiseksi
JP5944690B2 (ja) * 2012-02-23 2016-07-05 京セラ株式会社 配線基板の製造方法
JP6101151B2 (ja) * 2013-05-22 2017-03-22 日東電工株式会社 回路付きサスペンション基板およびその製造方法
WO2017142741A1 (en) * 2016-02-19 2017-08-24 Alpha Assembly Solutions Inc. Rf shield with selectively integrated solder
JP7248038B2 (ja) * 2018-12-06 2023-03-29 株式会社村田製作所 モジュールおよびその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3268653A (en) * 1964-04-29 1966-08-23 Ibm Printed circuit board with solder resistant coating in the through-hole connectors
US3568312A (en) * 1968-10-04 1971-03-09 Hewlett Packard Co Method of making printed circuit boards
US3576722A (en) * 1969-03-26 1971-04-27 Bendix Corp Method for metalizing ceramics
US3742597A (en) * 1971-03-17 1973-07-03 Hadco Printed Circuits Inc Method for making a coated printed circuit board
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
JPS5817651A (ja) * 1981-07-24 1983-02-01 Hitachi Ltd 多層回路板とその製造方法
US4546413A (en) * 1984-06-29 1985-10-08 International Business Machines Corporation Engineering change facility on both major surfaces of chip module
US4672739A (en) * 1985-04-11 1987-06-16 International Business Machines Corporation Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate

Also Published As

Publication number Publication date
EP0380289A3 (de) 1991-07-17
EP0380289B1 (de) 1997-09-10
CA2008284C (en) 1994-02-22
CA2008284A1 (en) 1990-07-24
EP0380289A2 (de) 1990-08-01
JPH0632367B2 (ja) 1994-04-27
US5061552A (en) 1991-10-29
JPH02194691A (ja) 1990-08-01

Similar Documents

Publication Publication Date Title
DE59400189D1 (de) Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE3671580D1 (de) Verfahren zum herstellen eines mehrschicht-keramiksubstrats.
DE69030229D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69033736T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69619602T2 (de) Verfahren zum Herstellen eines Halbleiter-Substrats
DE69031543T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69133316D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69022087T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE68910368T2 (de) Verfahren zum Herstellen eines Halbleiterkörpers.
DE68926656D1 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE69028964T2 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69023524D1 (de) Verfahren zum Herstellen einer Multischichtenverbindungsstruktur.
DE68928184T2 (de) Verfahren zum Herstellen eines keramischen Laminates
DE69024893D1 (de) Verfahren zum Herstellen einer Fotodiode
DE69031394D1 (de) Verfahren zum Herstellen eines keramischen Mehrschichtsubstrates
DE59409429D1 (de) Verfahren zum Herstellen eines Metall-Keramik-Substrates
DE69120975D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE69210646D1 (de) Verfahren zum Herstellen eines mehrschichtigen geformten Gegenstandes
DE69018884D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung.
DE69023745D1 (de) Oberflächenstruktur eines Keramiksubstrates und Verfahren zu deren Herstellung.
DE69116592T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE68917840D1 (de) Verfahren zum Herstellen einer dielektrischen Schicht.
DE69620946T2 (de) Verfahren zum Herstellen eines zylinderförmigen keramischen Gegenstandes
DE69128326T2 (de) Ein Verfahren zum Herstellen einer Halbleiteranordnung
DE69115387D1 (de) Verfahren zum Herstellen eines Glasgegenstandes

Legal Events

Date Code Title Description
8332 No legal effect for de